Consolidated chip design for wire bond and flip-chip package technologies

A semiconductor die configured to facilitate electrical connection of an external connector thereto through a plurality of metal bumps and a plurality of wire bond pads, said semiconductor die comprising:

• a semiconductor substrate having a region of active circuitry associated therewith and an overlying metallization level, said metallization level being electrically coupled to said region of active circuitry;
• an inter-level dielectric layer disposed over said metallization level, said inter-level dielectric layer having a plurality of grooves formed in an upper surface thereof, at least two of said plurality of grooves having an aperture formed therein exposing a portion of said metallization level, each groove being spaced from all other grooves of said plurality of grooves;
• a conductive metal filling each of said plurality of grooves and each of said corresponding apertures to form a plurality of final metallization lines and a plurality of integral corresponding studs, respectively, each of said plurality of final metallization lines having a wire bond pad, thereby defining a plurality of wire bond pads electrically coupled to said region of active circuitry through said plurality of final metallization lines and said plurality of corresponding studs, each wire bond pad of said plurality of wire bond pads being configured to facilitate electrical connection of an external connector thereto;
• an insulating material film disposed over said plurality of final metallization lines, said plurality of wire bond pads being exposed through a plurality of corresponding contact holes in said insulating material film, said insulating material film also having a plurality of via holes therein, each via hole being laterally displaced from a corresponding contact hole and exposing a portion of each underlying final metallization line laterally displaced from a corresponding exposed wire bond pad;
• and
• a plurality of metal bumps, each metal bump being disposed in a corresponding via hole, contacting a corresponding final metallization line, and being electrically interconnected thereby to a corresponding wire bond pad of said plurality of wire bond pads, each metal bump being laterally displaced from said corresponding wire bond pad and being configured to facilitate electrical connection of an external connector thereto, such that electrical connection to said region of active circuitry of said semiconductor substrate can occur through either said plurality of metal bumps or said plurality of wire bond pads.