Method and apparatus for programming anti-fuses

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising:

• a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a predetermined polarity;
• a second external terminal of the integrated circuit adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage;
• and
• a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive, the voltage translation circuit including,
• a control circuit which operates to couple the second external terminal to a pass terminal when the enable signal is active and to couple the second external terminal to a control terminal when the enable signal is inactive to thereby provide the second programming voltage on the pass and control terminals, respectively;
• a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active;
• and
• a reset circuit coupled to the enable terminal and the control terminal and having a reset terminal coupled to the input terminal of the pass circuit, the reset circuit operable to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the second programming voltage on the control terminal, and operable to isolate the reset terminal when the enable signal is inactive.

A programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising:

• a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a positive programming voltage;
• an external terminal of the integrated circuit adapted to receive a negative programming voltage;
• an enable terminal adapted to receive an enable signal;
• and
• a voltage translation circuit coupled to the external terminal, the enable terminal, and the second terminal of the anti-fuse, comprising,
• a control circuit which operates to couple the external terminal to a pass terminal when the enable signal is active and to couple the external terminal to a control terminal when the enable signal is inactive to thereby provide the negative programing voltage on the pass and control terminals, respectively,
• a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active, and
• a reset circuit having a reset terminal coupled to the input terminal of the pass circuit, operable in a first mode to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the negative programming voltage on the control terminal, and operable in a second mode to provide a high impedance at the reset terminal when the enable signal is active and no negative programming voltage is provided on the control terminal.

A dynamic random access memory, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a control circuit coupled the control bus;
• a read/write circuit coupled to the data bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• a programming circuit for programming an anti-fuse having first and second terminals, comprising,
• a first terminal of the dynamic random access memory coupled to the first terminal of the anti-fuse, the first external terminal adapted to receive a first programming voltage having a positive polarity,
• a second external terminal of the dynamic random access memory adapted to receive a second programming voltage having a negative polarity, and
• a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

A dynamic random access memory, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a control circuit coupled the control bus;
• a read/write circuit coupled to the data bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, and
• a programming circuit for programming an anti-fuse having first and second terminals, comprising,
• a first external terminal of the dynamic random access memory coupled to the first terminal of the anti-fuse, the first external terminal adapted to receive a first programming voltage having a predetermined polarity,
• a second external terminal of the dynamic random access memory adapted to receive a second programming voltage having a polarity opposite that of the first programming voltage, and
• a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive, the voltage translation circuit comprising,
• a control circuit which operates to couple the second external terminal to a pass terminal when the enable signal is active and to couple the second external terminal to a control terminal when the enable signal is inactive to thereby provide the second programming voltage on the pass and control terminals, respectively,
• a pass circuit having an input terminal coupled to the pass terminal and an output terminal coupled to the second terminal of the anti-fuse, the pass circuit operable to couple the input terminal to the output terminal when the enable signal is active, and
• a reset circuit having a reset terminal coupled to the input terminal of the pass circuit, operable in a first mode to drive the reset terminal to a reference voltage when the enable signal is inactive and the control circuit provides the negative programming voltage on the control terminal, and operable in a second mode to provide a high impedance at the reset terminal when the enable signal is active and no negative programming voltage is provided on the control terminal.

A computer system, comprising:

• a data input device;
• a data output device;
• and
• computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes a programming circuit for programming an anti-fuse having first and second terminals, the programming circuit and the anti-fuse being fabricated in the same integrated circuit, comprising,
• a first terminal of the integrated circuit coupled to the first terminal of the anti-fuse, the first terminal adapted to receive a first programming voltage having a positive polarity,
• a second external terminal of the integrated circuit adapted to receive a second programing voltage having a negative polarity;
• and
• a voltage translation circuit coupled between the second external terminal and the second terminal of the anti-fuse and having an enable terminal adapted to receive an enable signal, the voltage translation circuit operable to couple the second programming voltage to the second terminal of the anti-fuse in response to the enable signal being active and to isolate positive and negative voltages on the second external terminal from the second terminal of the anti-fuse when the enable signal is inactive.

A method for programming an anti-fuse having first and second terminals, comprising:

• applying a first programming voltage having a positive polarity to the first terminal of the anti-fuse;
• applying a second programming voltage having a negative polarity to an external terminal of an integrated circuit containing the anti-fuses;
• and
• coupling the second programming voltage to the second terminal of the anti-fuse in a first operating mode and isolating positive and negative voltages on the external terminal from the second terminal of the anti-fuse in a second operating mode.