Semiconductor component for high voltage
AssigneeTelefonaktiebolaet LM Ericsson
InventorsAnders Soderbarg, Per Svedberg
Life of this patent
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Abstract
A high frequency MOS transistor structure with an extended drift region, which modulates the resistance in the drift region of the MOS transistor. The extended gate layer is obtained by an extra semiconductor layer forming a second MOS structure on top of a thin gate oxide layer. The electrical field will then be uniformly distributed laterally in the extended drift region. This design makes it possible to produce a MOS transistor with a short channel length and an extended drift region with low doping concentration and still having very low on-resistance together with a high breakdown voltage.
Claims18
A device forming a high voltage MOS transistor structure comprising a substrate with a n.sup.- doped semiconductor layer having a first n.sup.+ doped drain area and a p doped body containing a second n.sup.+ doped region and a first p.sup.+ doped region forming a source area, said n.sup.- doped layer providing a drift channel between said drain and source areas, wherein on top of said drift channel an insulating gate oxide layer is disposed having on top a semiconductor layer which together with the insulating gate oxide layer forms an extended gate layer, whereby a diode is connected between said drain area and a third n.sup.+ doped region in said extended gate layer.
A device forming a high voltage MOS transistor structure comprising a substrate with a p.sup.- doped semiconductor layer having a first p.sup.+ doped drain area and a n doped body containing a second p.sup.+ doped region and first n.sup.+ doped region forming a source area, said p.sup.- doped layer providing a drift channel between said drain and source areas, wherein on top of said drift channel an insulating gate oxide layer is disposed having on top a semiconductor layer which together with the insulating gate oxide layer forms an extended gate layer, whereby a diode is connected between said drain area a third p.sup.+ doped region in said extended gate layer.
Dependencies are inferred from the claim text.