Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsJunichiro Noda, Daisuke Tohyama
Life of this patent
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Abstract
A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.
Claims25
A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate with an element region and an isolation region;
- a select MOS transistor formed in said element region;
- and
- a data storage MOS transistor which is formed in said element region and which includes a source region, a drain region, a floating-gate electrode, and a control gate electrode, said floating-gate electrode having a first portion above said drain region and a second portion above said semiconductor substrate between said source region and said drain region, an insulating film thinner than a gate insulating film of said select MOS transistor being arranged between said drain region and said first portion of said floating-gate electrode and between said semiconductor substrate and said second portion of said floating-gate electrode, and said first and second portions of said floating-gate electrode being spaced apart above said element region, and connected to each other on said isolation region.
A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising:
- a semiconductor substrate of a first conductivity type;
- first, second, and third impurity regions of a second conductivity type formed in said semiconductor substrate;
- a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions;
- a floating gate electrode of said data storage transistor having a first electrode portion provided over at least a portion of said second impurity region, and a second electrode portion, spaced apart from said first electrode portion, provided over a second channel region between said second impurity region and said third impurity region;
- a first insulating film formed between said first electrode portion of said floating gate electrode and said at least a portion of said second impurity region and between said second electrode portion of said floating gate electrode and said second channel region;
- and
- a second insulating film formed between said gate electrode of said selection transistor and said first channel region,
- wherein the thickness of said first insulating film is less than the thickness of said second insulating film.
A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising:
- a semiconductor substrate of a first conductivity type;
- first, second, and third impurity regions of a second conductivity type formed in said semiconductor substrate;
- a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions;
- a floating gate electrode of said data storage transistor having a first electrode portion provided at least partly over a first portion of said second impurity region having a first impurity concentration and a second electrode portion provided over a second channel region between a second portion of said second impurity region having a second impurity concentration and said third impurity region.
A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising:
- a semiconductor substrate of a first conductivity type;
- first, second, and third impurity regions of a second conductivity type formed in said semiconductor substrate;
- a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions;
- a floating gate electrode of said data storage transistor having a first electrode portion provided at least partly over a first portion of said second impurity region having a first impurity concentration and a second electrode portion provided over a second channel region between a second portion of said second impurity region having a second impurity concentration and said third impurity region;
- a first insulating film formed between said first channel region and said gate electrode;
- and
- a second insulating film formed between said first electrode portion of said floating gate electrode and said second impurity region and between said second electrode portion of said floating gate electrode and said second channel region,
- wherein said second insulating film is thinner than said first insulating film, and
- wherein the second impurity concentration is at least several times lower than the first impurity concentration.
Dependencies are inferred from the claim text.