Semiconductor device comprising polysilicon interconnection layers separated by insulation films

A semiconductor device comprising:

• multiple pairs of bit lines;
• multiple memory cells that are connected between the individual pairs of bit lines and are driven by a common word line;
• a power supply line for supplying power supply voltage to said multiple memory cells;
• a common current path that is connected to said power supply line and that supplies current to said multiple memory cells;
• a reverse-direction diode within said common current path;
• and
• an interconnection layer that connects said common current path with said memory cells;
• and
• wherein one of the memory cells comprises:
• a pair of N-type insulation gate field effect transistors that constitute a flip-flop;
• a pair of N-type insulation gate field effect transistors that constitute a transfer gate provided between two output terminals of said flip-flop and a pair of bit lines;
• and
• a pair of P-type insulation gate field effect transistors that constitute a load of said flip-flop and that are provided between a common connection point between the output terminals of said flip-flop and the insulation gate field effect transistors that constitute said transfer gate, and the power supply line;
• and
• wherein a source layer and a drain layer of the pair of N-type insulation gate field effect transistors that constitute said flip-flop, and a source layer and a drain layer of the pair of N-type insulation gate field effect transistors that constitute said transfer gate are impurity layers formed inside a semiconductor substrate;
• wherein the source (S) and the drain (D) of the pair of P-type insulation gate field effect transistors that constitute the load of said flip-flop comprise an n-th P-type polycrystalline silicon layer, where n is an integer of at least 2, formed on a semiconductor substrate, and said n-th P-type polycrystalline silicon layer that exists continuously to said source (S) acts both as an interconnection between said common current path and each of said memory cells and as an interconnection that constitutes part of said common current path;
• wherein said pair of bit lines and said common current path are located in conductive layers both of which are higher than said n-th polycrystalline silicon layer;
• wherein said pair of bit lines and the drain layer of the N-type insulation gate field effect transistors that constitute said transfer gate are mutually connected by the first relay line that is formed using the (n-1)-th N-type polycrystalline silicon layer:
• wherein the n-th P-type polycrystalline silicon layer that acts as said interconnection and said common current path are mutually connected by a second relay line that is formed using the (n-1)-th N-type polycrystalline silicon layer, and thus forming a reverse-direction diode within said common current path;
• wherein the thickness of said (n-1)-th N-type polycrystalline silicon layer that constitutes said second relay line is thicker than the thickness of said n-th P-type polycrystalline silicon layer that acts as said interconnection;
• and
• wherein the density distribution of N-type impurities in the thickness direction in the region, in which said reverse-direction diode is formed of the (n-1)-th N-type polycrystalline silicon layer that constitutes said second relay line peaks near the function of said reverse-direction diode;
• and
• wherein said N-type impurity for said (n-1)-th N-type polycrystalline silicon layer that constitutes said second relay line comprises arsenic (As) introduced through ion implantation;
• and
• wherein an acceleration speed used for implanting arsenic (As) ions into said (n-1)-th N-type polycrystalline silicon layer that constitutes said second relay line is in a range between 40 and 70 KeV, and the dose is in a range of 3.times.10.sup.15 atms/cm.sup.2 to 1.times.10.sup.16 atms/cm.sup.2.