Method and apparatus for providing dynamically variable time delays for ultrasound beamformer

A beamformer comprising a multiplicity of beamformer channels and a summer having a multiplicity of inputs respectively coupled to said multiplicity of beamformer channels, wherein each of said beamformer channels comprises:

• analog-to-digital conversion means for outputting digital samples at a sampling rate;
• an integer sampling period delay circuit having an input coupled to receive said digital samples and having an output;
• a fractional sampling period delay circuit having an input coupled to receive said digital samples from said integer sampling period delay circuit and having an output coupled to a respective input of said summer;
• and
• a delay control circuit coupled to said integer sampling period delay circuit and to said fractional sampling period delay circuit for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit and said fractional sampling period delay circuit will respectively delay a signal passing therethrough,
• wherein said integer sampling period delay circuit comprises a FIFO having an input coupled to receive said digital samples and having an output, and a first register having an input coupled to said output of said FIFO and having an output, said fractional sampling period delay circuit comprises an interpolator having a first input coupled to said output of said first register and said delay control circuit comprises means for holding the contents of said first register to keep said output of said first register synchronized with said output of said FIFO following a change in the amount of delay provided by said FIFO.

An ultrasonic imaging system comprising a transducer array, a beamformer coupled to said transducer array, a signal processor coupled to said beamformer, a scan converter coupled to said signal processor, and a display monitor coupled to said scan converter, wherein said transducer array comprises a multiplicity of transducer elements and said beamformer comprises a multiplicity of beamformer channels, switching circuitry for selectively coupling said beamformer channels to said transducer elements, and summing means having a multiplicity of inputs respectively coupled to said multiplicity of beamformer channels, wherein each of said beamformer channels comprises:

• analog-to-digital conversion means for outputting digital samples at a sampling rate;
• an integer sampling period delay circuit having an input coupled to receive said digital samples and having an output;
• a fractional sampling period delay circuit having an input coupled to receive said digital samples from said integer sampling period delay circuit and having an output coupled to a respective input of said summer;
• and
• a delay control circuit coupled to said integer sampling period delay circuit and to said fractional sampling period delay circuit for outputting delay signals which dynamically synchronously control the amount by which said integer sampling period delay circuit and said fractional sampling period delay circuit will respectively delay a signal passing therethrough,
• wherein said integer sampling period delay circuit comprises a FIFO having an input coupled to receive said digital samples and having an output, a first register having an input coupled to said output of said FIFO and having an output, and a second register having an input coupled to said output of said first register and having an output, said fractional sampling period delay circuit comprises an interpolator having first and second inputs respectively coupled to said outputs of said first and second registers, and said delay control circuit comprises means for holding the contents of said first and second registers to keep said outputs of said first and second registers synchronized with said output of said FIFO following a change in the amount of delay provided by said FIFO.

A method of generating a time-delayed digital sample in an ultrasound beamformer corresponding to a digital sample having a time delay which is a fraction of a sampling period, comprising the steps of:

• acquiring first and second digital samples of an ultrasound receive signal in first and second sampling periods;
• bit shifting and inverting said first and second digital samples in accordance with a first set of interpolation coefficients to produce a first multiplicity of bit shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said first set of interpolation coefficients;
• adding said first multiplicity of bit shifted and inverted digital samples to produce a first interpolated digital sample;
• bit shifting and inverting said first through fourth digital samples in accordance with a second set of interpolation coefficients to produce a second multiplicity of bit shifted and inverted digital samples which are dependent on the results of shifting and inverting said first and second digital samples from said first and second registers in accordance with said second set of interpolation coefficients;
• adding said second multiplicity of bit shifted and inverted digital samples to produce a second interpolated digital sample;
• and
• multiplexing one of said first and second interpolated digital samples to an output.

A beamforming channel comprising:

• analog-to-digital conversion means for outputting digital samples at a sampling rate;
• a FIFO having an input coupled to receive said digital samples and having an output;
• first through N-th registers connected in series, said first register having an input coupled to said output of said FIFO and having an output, and said N-th register having an input and an output;
• an interpolator having first through N-th inputs respectively coupled to said outputs of said first through N-th registers;
• and
• a delay control circuit coupled to said FIFO, to said first through N-th registers and to said interpolator for outputting delay signals which dynamically synchronously control the amount of delay of a signal passing through said FIFO, said registers and said interpolator, wherein said delay control circuit comprises means for holding the contents of said first through N-th registers to keep said outputs of said first through N-th registers synchronized with said output of said FIFO following a change in the amount of delay provided by said FIFO.