Tunneling technology for reducing intra-conductive layer capacitance

A method of manufacturing a semiconductor device comprising:

• forming an insulating layer on a substrate;
• forming a conductive pattern on the insulating layer, wherein the conductive pattern comprises conductive lines separated by interwiring spaces;
• depositing a dielectric liner in the interwiring spaces in which air tunnels are formed to cover the conductive lines and substrate;
• depositing spin on glass in the interwiring spaces in which air tunnels are to be formed and on the conductive lines, and curing the deposited spin on glass;
• depositing a dielectric capping layer on and across the dielectric liner and across the interwiring spaces filled with spin on glass;
• selectively positioning a mask at locations of the conductive pattern having an interwiring spacing of less than about 1 micron, wherein the mask contains at least two openings for defining locations at the beginning and end of air tunnels;
• etching to remove spun on glass, thereby forming air spaces in the interwiring spaces;
• and
• depositing a dielectric layer over the air spaces thereby forming air tunnels in the interwiring spaces of less than about 1 micron.