US 5,843,826 AGranted

Deep submicron MOSFET device

AssigneeUnited Microeletronics Corp.

InventorGary Hong

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Abstract

A FET is formed that occupies a reduced surface area on a substrate because it incorporates elevated source/drain contacts provided at least partially over the field oxide regions. A silicon nitride mask is formed over the substrate and the mask is used for defining field oxide regions. Trenches are etched on either side of the mask and then thermal oxidation grows field oxide regions in the trenches so that the surface of the field oxide regions are approximately even with the original surface of the substrate. With the silicon nitride mask still in place, polysilicon is deposited over the substrate. The device is then planarized to remove the polysilicon from surfaces of the substrate, exposing the surface of the mask and leaving polysilicon structures on the field oxide regions on either side of mask. The mask is stripped and a layer of silicon is deposited over the polysilicon structures and on the active device region of the substrate, where the deposited silicon is epitaxial. A gate oxide layer is formed by oxidation of the epitaxial silicon and then a gate electrode is formed. The gate electrode can be spaced closer to the field oxide regions than is typically possible because contacts to the source/drain regions of the FET are formed through the first and second conductive structures.

Claims12

Dependent claims

A method of forming an integrated circuit device comprising the steps of:

providing a substrate having first and second insulating device isolation structures on a surface of the substrate, a portion of the surface of the substrate between the first and second insulating device isolation structures providing at least a portion of an active device region for the integrated circuit device;
forming first and second conductive structures on the corresponding first and second device isolation structures;
depositing a layer of silicon material over the active device region and connecting the first and second conductive structures to portions of the active device region;
forming a gate oxide layer and a gate electrode on the layer of silicon over the active device region, the gate electrode positioned at least partially between the first and second conductive structures;
and
forming first and second source/drain regions at least partially within the layer of silicon over the active device region, the first and second conductive structures electrically connected to and providing contacts for the respective first and second source/drain regions;
wherein the device isolation structures are provided by forming a mask over the substrate and providing insulating device isolation regions aligned with first and second edges of the mask;
and
wherein the step of forming first and second conductive structures includes the steps of:
depositing a polysilicon layer over surfaces of the first and second insulating device isolation regions and over the mask;
and
planarizing the polysilicion layer so that the polysilicon layer is removed from over the mask and first and second polysilicon structures extend over the first and second insulating device isolation structures on either side of the mask.

9 more elements

Dependencies are inferred from the claim text.