US 5,843,821 AGranted

Fabrication method for a cylindrical capacitor for a semiconductor device

AssigneeVanguard International Semiconductor Corporation

InventorHorng-Huei Tseng

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Abstract

The present invention provides a method of manufacturing a capacitor for a high density memory device. The capacitor has a bottom electrode 70 having cylindrical walls 54A more closely spaced than the minimum photolithography dimensions. The method begins by providing a first conductive layer 30 that contacts the substrate. A polyoxide layer 36A is used to form an opening over the first conductive layer 30 that defines a dielectric stud 50. An important feature is the polyoxide layer 36A makes the opening 38A smaller than the photolithographic limits. Cylindrical walls 54A are formed on the sidewalls of the dielectric stud 50. Subsequent etches are used to form the bottom electrode 54A, 30B (70). The electrode of the present invention is smaller than the conventional minimum photo ground rules and the method is cost effective and highly manufacturable.

Claims8

Dependent claims

A method of fabricating a capacitor of a semiconductor memory cell on a substrate having an active area, comprising the steps of:

a) forming a planarized first insulating layer over said substrate, said substrate having the active area;
b) forming a first opening in said first insulating layer exposing said active area;
c) forming a first conductive layer over said first insulating layer and filling said first opening and contacting said active area;
d) forming an oxidation barrier layer over said first conductive layer;
e) forming a polysilicon layer over said oxidation barrier layer;
f) forming a second opening, using a photolithographic process, in said polysilicon layer;
said second opening having an open dimension of a minimum photolithography dimension, a minimum size of a capability of said photolithographic process;
g) oxidizing said polysilicon layer forming a polyoxide layer;
and said polyoxide layer redefining said second opening as a third opening;
said third opening having a smaller open dimension than said second opening;
h) anisotropically etching said oxidation barrier layer and said first conductive layer using said third opening as an etch mask and forming an electrode center hole extending at least partially through said first conductive layer;
said electrode center hole having an open dimension smaller than the minimum photolithography dimension;
i) removing said polyoxide layer;
j) forming a first dielectric layer over said oxidation barrier layer and filling said electrode center hole;
k) removing said first dielectric layer over said oxidation barrier layer forming a dielectric stud filling said electrode center hole;
said dielectric stud having sidewalls;
l) removing said oxidation barrier layer and removing a portion of said first conducting layer using an anisotropically etch;
m) forming a second conducting layer over said remaining first conducting layer and said dielectric stud;
n) anisotropically etching said second conducting layer forming upper electrodes on said sidewalls of said dielectric stud;
and anisotropically etching said first conductive layer exposing said first insulating layer;
the remaining first conductive layer under said upper electrodes and said dielectric stud forming a bottom plug;
said bottom plug and said upper electrodes forming a bottom electrode;
o) removing said dielectric stud;
p) forming a capacitor dielectric layer over said bottom electrode;
and
q) forming a top electrode over said capacitor dielectric layer.

23 more elements

A method of fabricating a capacitor of a semiconductor memory cell on a substrate having an active area, comprising the steps of:

a) forming a planarized first insulating layer over said substrate;
said substrate having the active area;
said first insulating layer is composed of a material selected from the group consisting of undoped oxide, phosphosilicate glass, borosilicate glass (BSG), and borophosphosilicate glass;
said first insulating layer having a thickness in a range of between about 3000 and 8000 .ANG.;
b) forming a first opening in said first insulating layer exposing said active area;
c) forming a first conductive layer over said first insulating layer and filling said first opening and contacting said active area;
said first conductive layer composed of doped polysilicon and having a thickness in a range of between about 4000 and 10,000 .ANG.;
d) forming an oxidation barrier layer over said first conductive layer;
said oxidation barrier layer composed of silicon nitride;
and has a thickness in a range of between about 100 and 400 .ANG.;
e) forming a polysilicon layer over said oxidation barrier layer;
said polysilicon layer having a thickness in a range of between about 1000 and 4000 .ANG.;
f) forming a second opening in said polysilicon layer;
said second opening having an open dimension of a minimum photolithography dimension, a minimum size of a capability of said photolithographic process;
g) oxidizing said polysilicon layer forming a polyoxide layer;
and said polyoxide layer redefining said second opening as a third opening;
said third opening having a smaller open dimension than said second opening;
h) anisotropically etching said oxidation barrier layer and said first conductive layer using said third opening as an etch mask and forming an electrode center hole extending at least partially through said first conductive layer;
said electrode center hole having an open dimension smaller than the minimum photolithography dimension;
said electrode center hole having a depth into said first conductive layer in a range of between about 3000 and 8000 .ANG.;
i) removing said polyoxide layer;
j) forming a first dielectric layer over said oxidation barrier layer and filling said electrode center hole;
said first dielectric layer having a thickness in a range of between about 500 and 2000 .ANG.;
k) removing said first dielectric layer over said oxidation barrier layer forming a dielectric stud filling said electrode center hole;
said dielectric stud having sidewalls;
said first dielectric layer over said oxidation barrier layer is removed using a chemical-mechanical polish process;
l) removing said oxidation barrier layer and removing a portion of said first conducting layer using an anisotropically etch;
the remaining first conducting layer having a thickness over said first insulating layer in a range of between about 2000 and 3000 .ANG.;
m) forming a second conducting layer over said remaining first conducting layer and said dielectric stud;
said second conducting layer having a thickness in a range of between about 500 and 2000 .ANG.;
and composed of doped polysilicon;
n) anisotropically etching said second conducting layer forming upper electrodes on said sidewalls of said dielectric stud;
and anisotropically etching said first conductive layer exposing said first insulating layer;
the remaining first conductive layer under said upper electrodes and said dielectric stud forming a bottom plug;
said bottom plug and said upper electrodes forming a bottom electrode;
o) removing said dielectric stud;
p) forming a capacitor dielectric layer over said bottom electrode;
and
q) forming a top electrode over said capacitor dielectric layer.

36 more elements

Dependencies are inferred from the claim text.