Ternary CAM memory architecture and methodology

A method of storing ternary data, comprising the steps of:

• initializing a binary-to-ternary conversion register by storing binary-to-ternary mask data in the binary-to-ternary conversion register, wherein the binary-to-ternary mask data comprises information relating to the location of don't care bits for input data;
• inputting a single bit of binary data to the binary-to-ternary conversion register;
• converting the single bit of binary data into first and second ternary data outputs using the binary-to-ternary conversion register;
• and
• simultaneously storing as stored content addressable memory (CAM) data the first and second ternary data outputs in first and second memory cells forming a content addressable memory.

A memory system comprising:

• a binary-to-ternary conversion register;
• and
• means for initializing the binary-to-ternary conversion register, comprised of:
• means for storing binary-to-ternary mask data in the binary-to-ternary conversion register, said binary-to-ternary mask data comprising information relating to the location of don't care bits for input data;
• a content addressable memory (CAM) comprising at least first and second memory cells for storing ternary data;
• means for storing the ternary data in the CAM, comprising:
• means for inputting a single bit of binary data to the conversion register;
• means for converting the binary data into two bits of ternary data using the conversion register;
• and
• means for simultaneously storing as stored CAM data the two bits of ternary data in the
• first and second memory cells of the CAM.

A memory system for providing secure asynchronous transfer mode (ATM) communications for an ATM network that transmits a plurality of data cells, each of the plurality of data cells comprising payload data and header data comprised of virtual path identifier (VPI) address data and virtual channel identifier (VCI) address data, the memory system receiving a plurality of data input signals, encryption VPI and VCI addresses, and associate key data signals, the memory system comprising:

• a ternary content addressable memory (TCAM) subsystem for storing a first one of the data input signals as stored ternary data, and for determining a match output address by comparing another one of the data input signals to the stored ternary data;
• an addressable lookup table subsystem for storing the key data signals and selectively outputting the key data signals in accordance with the match output address;
• wherein the TCAM subsystem and the addressable lookup table subsystem form a memory subsystem;
• means for initializing the memory subsystem comprising:
• means for storing the encryption VPI and VCI addresses in the TCAM subsystem;
• means for storing the key data associated with the encryption VPI and VCI addresses in the lookup table;
• means for separating the payload data from the header data for each of the data cells;
• means for delivering the separated header data to the TCAM, wherein the TCAM selectively outputs the match output address when the separated header data matches one of the stored VPI and VCI addresses;
• wherein the lookup table outputs the key data associated with the respective match output address;
• means for encrypting the payload data in accordance with the key data;
• and
• means for combining the encrypted payload data with the separated header data to form an encrypted data cell.

A memory system for implementing a secure asynchronous transfer mode (ATM) communication system that transmits a plurality of signals comprising associated encryption key data, virtual path identifier (VPI) data, virtual channel identifier (VCI) data, and data cells, each data cell comprising payload data and header data, said header data comprised of VPI/VCI data, wherein respective ones of the encryption key data are associated with respective ones of the VPI/VCI data, the memory subsystem comprising:

• a content addressable memory (CAM) subsystem for storing data therein;
• an addressable lookup table;
• a processor for storing VPI/VCI data into the CAM subsystem, each at a respective storage address, and for storing the respective associated encryption key data into the lookup table at a location mapped to the respective storage address;
• a decoder for separating the header data from the payload data for each of the data cells;
• wherein the CAM subsystem includes means for comparing the stored data therein to the separated header data to selectively determine a match address output when the separated header matches any of the stored data therein;
• wherein the lookup table outputs the associated encryption key data based on the match address output;
• an encryptor for encrypting the separated payload data based on the encryption key data output from the lookup table;
• and
• a combiner for combining the encrypted payload data with the separated header to form an encrypted data cell.

A memory apparatus, comprising:

• a plurality of memory locations each capable of storing at least one data record having multiple bit positions;
• means for receiving data records from an exterior environment for storage in said plurality of memory locations;
• means for storing said received data records in said plurality of memory storage locations;
• means for receiving a search data record from an exterior environment for comparison with data records stored in said plurality of memory locations;
• means for comparing said search data record to multiple data records stored in said plurality of memory locations, to determine whether a record match exists between said search data record and one of the multiple data records, said comparing means comparing each bit position of said search data record to a corresponding bit position in each of said multiple data records;
• means for storing first don't care bits in selected bit positions within said multiple data records stored in said plurality of memory locations, said first don't care bits each resulting in a bit match when compared with data bits in said search data record irrespective of the content of said search data record;
• and
• means for adding second don't care bits to selected bit positions in said search data record, said second don't care bits each resulting in a bit match when compared to data bits in said multiple data records irrespective of the content of said multiple data records.