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US 5,841,674 AGranted
Circuit design methods and tools
AssigneeViewlogic Systems, Inc.
InventorDavid L. Johannsen
Life of this patent
Estimating the term…
Abstract
A circuit design tool which includes an architecture for a multiplier which is faster and more compact than known multipliers through the use of Wallace trees, the elimination of Dadda nodes along the critical paths, the placement of half-adders at an initial pat of the Wallace tree, the replacement of low-order terminating adders with ripple-carry adders, and the replacement of high-order terminating adders with carry-select adders.
Claims5
A method for the operation of a circuit design tool to design a multiplier circuit, comprising the steps of
- forming a netlist for a Wallace tree, whereby said Wallace tree comprises a tail of adders;
- tracing a critical path for said netlist to a Dadda node in said Wallace tree and eliminating said Dadda node by replacing said Dadda node with a full-adder;
- placing a half-adder at an initial part of said Wallace tree and removing an adder in said tail;
- and
- repeating said steps of tracing and placing until a selected condition is reached.
2 more elements
Dependencies are inferred from the claim text.