Locally asynchronous, pipeline-able logic circuits for true-single-phase synchronous logic circuit

In a pipeline-able asynchronous logic circuit that implements a subfunction of a logic function that is distributed into multiple sequential subfunctions, each subsequent subfunction being applied to a result of an immediately preceding subfunction of said sequence, a method comprising the steps of:

• applying a particular subfunction to an inputted signal to produce a result signal in a differential logic circuit,
• only in response to enabling a sense amplifier, using said sense amplifier to amplify said result signal produced by said differential logic circuit in said sense amplifier and outputting said amplified result signal from said sense amplifier onto an output node,
• only when said sense amplifier is disabled, using a pre-charge circuit to pre-charge said output node to a first voltage,
• in response to receiving an enable signal at a first enable circuit, using said first enable circuit to enable said sense amplifier and outputting said enable signal only when sense amplifier outputs said amplified result signal,
• in response to receiving said enable signal at a second enable circuit, using said second enable circuit to enable said differential logic circuit, and
• if a logic value of said result signal corresponds to said first voltage, charging said output node from said differential logic circuit via a first path and charging said output node from said sense amplifier charges via a second path, distinct from said first path, to a second voltage of opposite polarity with respect to said first voltage.

A synchronous logic circuit for applying a logic function that is distributed into multiple sequential subfunctions, each subsequent subfunction being applied to a result of an immediately preceding subfunction of said sequence comprising:

• a sequence of plural logic circuits that are serially connected together, each of said logic circuits comprising:
• an output node,
• a differential logic circuit connected to said output node via a first path, for applying a particular subfunction to an inputted signal to produce a result signal,
• a sense amplifier, connected to said output node via a second path that is distinct from said first path, which, in response to being enabled, amplifies said result signal produced by said differential logic circuit and outputs said amplified result signal onto said output node,
• a pre-charge circuit which pre-charges said output node to a first voltage, but only when said sense amplifier is disabled, and
• a first enable circuit which responds to receiving an enable signal by enabling said sense amplifier and outputting said enable signal only when sense amplifier outputs said amplified result signal,
• wherein said differential logic circuit drives said output node via said first path, and said sense amplifier drives said output node via said second path to a voltage corresponding to said result signal,
• wherein a first logic circuit of said sequence receives a clock signal, as said enable signal, and an initial input signal on which said logic function is applied, as said inputted signal, and each other logic circuit receives, as said enable signal, an output enable signal generated by the preceding logic circuit, and as said inputted signal, said result signal generated by said preceding logic circuit, and
• a latch circuit for storing a result produced by a last logic circuit of said sequence of logic circuits.