Single chip modules, repairable multichip modules, and methods of fabrication thereof

A multichip module comprising:

• a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;
• a structural material surrounding the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said plurality of chips to form a second surface, said second surface comprising a back surface;
• an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto;
• and
• wherein said structural material has a thickness equal to a thickest chip of said plurality of chips such that the upper surface of the structural material is substantially co-planar with the upper surface of the thickest chip to form said first substantially co-planar surface, and such that a lower surface of the structural material is substantially co-planar with a lower surface of said thickest chip of said plurality of chips to form a second substantially co-planar surface, said second substantially co-planar surface comprising said back surface.

A multichip module comprising:

• a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;
• a structural material surrounding the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said Plurality of chips to form a second surface, said second surface comprising a back surface;
• an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto;
• and
• wherein each chip of said plurality of chips has a common thickness, and wherein said structural material surrounding and mechanically interconnecting said chips in spaced planar relation comprises a thickness equal to said common thickness of said plurality of chips such that said second surface comprises a second substantially co-planar surface wherein the lower surface of said structural material is substantially co-planar with the lower surface of each chip of said plurality of chips, and wherein said first substantially co-planar surface comprising said front surface is parallel to said second substantially co-planar surface comprising said back surface.

A multichip module comprising:

• a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, a lower surface, and at least one contact pad at said upper surface;
• a structural material surrounding the at least one side surface of each chip of said plurality of chips and mechanically interconnecting in spaced, planar relation said plurality of chips, said structural material having an upper surface substantially co-planar with an upper surface of each chip of said plurality of chips to form a first substantially co-planar surface, said first substantially co-planar surface comprising a front surface, and such that a lower surface of said structural material is substantially parallel with a lower surface of each chip of said plurality of chips to form a second surface, said second surface comprising a back surface;
• an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material mechanically interconnecting said plurality of chips, said in situ processed layer including via openings to at least some contact pads at the upper surfaces of said plurality of chips for electrical connection thereto;
• wherein each chip of said Plurality of chips comprises a bare integrated circuit chip;
• and
• wherein each chip of said plurality of chips has an equal thickness such that the upper surface of each chip is co-planar with said front surface and the lower surface of each chip is co-planar with said back surface, said back surface comprising a planar main surface of the multichip module.

An integrated circuit chip module comprising:

• an integrated circuit chip comprising a bare chip having a substrate, active circuitry associated with said substrate, an upper surface and a lower surface, said integrated circuit chip further comprising multiple electrical contact pads at said upper surface electrically coupled to said active circuitry, said integrated circuit chip further having at least one side with a width defined by said upper surface and said lower surface;
• a structural material surrounding and physically contacting said at least one side of said integrated circuit chip, said structural material having a top surface substantially co-planar with said upper surface of said integrated circuit chip to form a first surface, said first surface comprising a front surface, and said structural material having a bottom surface substantially parallel with said lower surface of said integrated circuit chip to form a second surface, said second surface comprising a back surface;
• an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material surrounding said at least one side of said integrated circuit chip, said in situ processed layer including at least one via opening to at least one contact pad of said multiple electrical contact pads at the upper surface of said integrated circuit chip;
• and
• a metallization structure comprising metallization disposed within said at least one via opening electrically connecting to said at least one contact pad of said integrated circuit chip.

An integrated circuit chip module comprising:

• an integrated circuit chip comprising a bare chip having a substrate, active circuitry associated with said substrate, an upper surface and a lower surface, said integrated circuit chip further comprising multiple electrical contact pads at said upper surface electrically coupled to said active circuitry, said integrated circuit chip further having at least one side with a width defined by said upper surface and said lower surface;
• a structural material surrounding said at least one side of said integrated circuit chip, said structural material having a top surface substantially co-planar with said upper surface of said integrated circuit chip to form a first surface, said first surface comprising a front surface, and said structural material having a bottom surface substantially parallel with said lower surface of said integrated circuit chip to form a second surface, said second surface comprising a back surface;
• an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material surrounding said at least one side of said integrated circuit chip, said in situ processed layer including at least one via opening to at least one contact pad of said multiple electrical contact pads at the upper surface of said integrated circuit chin;
• a metallization structure comprising metallization disposed within said at least one via opening electrically connecting to said at least one contact pad of said integrated circuit chip;
• wherein said in situ processed layer comprises a photo-patternable dielectric material;
• and
• wherein said bottom surface is substantially co-planar with said lower surface of said integrated circuit chip.

An integrated circuit chip module comprising:

• an integrated circuit chip comprising a bare chip having a substrate, active circuitry associated with said substrate, an upper surface and a lower surface, said integrated circuit chip further comprising multiple electrical contact pads at said upper surface electrically coupled to said active circuitry, said integrated circuit chip further having at least one side with a width defined by said upper surface and said lower surface;
• a structural material surrounding said at least one side of said integrated circuit chip, said structural material having a top surface substantially co-planar with said upper surface of said integrated circuit chip to form a first surface, said first surface comprising a front surface, and said structural material having a bottom surface substantially parallel with said lower surface of said integrated circuit chip to form a second surface, said second surface comprising a back surface;
• an in situ processed layer disposed on said front surface, said in situ processed layer comprising a material different from said structural material surrounding said at least one side of said integrated circuit chip, said in situ processed layer including at least one via opening to at least one contact pad of said multiple electrical contact pads at the upper surface of said integrated circuit chip;
• a metallization structure comprising metallization disposed within said at least one via opening electrically connecting to said at least one contact pad of said integrated circuit chip;
• wherein said in situ Processed layer comprises a photo-patternable dielectric material;
• and
• wherein said back surface comprises an exposed planar main surface of said integrated circuit chip module.

A multichip module comprising:

• a plurality of chips, each chip comprising an unpackaged chip having at least one side surface, an upper surface, and a lower surface:
• structural material surrounding the at least one side surface of each chip of said Plurality of chips to mechanically interconnect in spaced planar relation said plurality of chips, said structural material having an upper surface co-planar with the upper surfaces of said plurality of chins, wherein a co-planar front surface is defined thereby, and wherein a lower surface of said structural material is substantially parallel with the lower surfaces of the plurality of chips, thereby defining a back surface;
• and
• wherein the lower surface of the structural material is substantially co-planar with the lower surfaces of the plurality of chips.