Back to results
US 5,841,175 AGranted
Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsSouichi Sugiura, Masaru Koyanagi
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.
Claims39
A semiconductor device comprising:
- a semiconductor substrate;
- a well region of a first conductivity type formed in said semiconductor substrate, said well region including a first portion of the first conductivity type having a first surface impurity concentration and a second portion of the first conductivity type having a second surface impurity concentration higher than the first surface impurity concentration;
- and
- insulated-gate field-effect transistors formed in said well region, each of said insulated-gate field-effect transistors having a channel region and the channel region of a first one of said insulated-gate field-effect transistors formed in said first portion of said well region and the channel region of a second one of said insulated-gate field effect transistors formed in said second portion of said well region.
1 more element
A semiconductor device, comprising:
- a semiconductor substrate;
- a well region of a first conductivity type formed in said semiconductor substrate, wherein a junction between said well region and said semiconductor substrate is at a first depth below a first surface portion of said well region having a first impurity concentration and is at a different second depth below a second surface portion of said well region having a second impurity concentration lower than the first impurity concentration;
- a first transistor having a channel region formed in said first surface portion of said well region;
- and
- a second transistor having a channel region formed in said second surface portion of said well region.
2 more elements
A semiconductor device, comprising:
- a semiconductor substrate;
- a first well region formed in said semiconductor substrate, wherein a junction between said first well region and said semiconductor substrate is at a first depth below a surface portion of said first well region having a first impurity concentration;
- a second well region formed in said semiconductor substrate, wherein a junction between said second well region and said semiconductor substrate is at a second depth below a first surface portion of said second well region having a second impurity concentration and is at a third depth different than the second depth below a second surface portion of said second well region having a third impurity concentration lower than the second impurity concentration;
- a first transistor including a channel region, a source region and a drain region formed in aid surface portion of said first well region;
- and
- a second transistor including a channel region formed in said second surface portion of said second well region and a source region and a drain region formed in said first surface portion of said second well region.
3 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a well region formed in said semiconductor substrate, wherein a junction between said well region and said semiconductor substrate is at a first depth below a first surface portion of said well region having a first impurity concentration and is at a different second depth below a second surface portion of said well region having a second impurity concentration lower than the first impurity concentration;
- a first transistor including a channel region formed in said second surface portion of said well region;
- and
- a second transistor including a channel region formed in said second surface portion of said well region,
- wherein said channel regions of said first and second transistors are aligned with each other.
3 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a well region formed in said semiconductor substrate, wherein a junction between said well region and said semiconductor substrate is at a first depth below a first surface portion of said well region having a first impurity concentration and is at a different second depth below a second surface portion of said well region having a second impurity concentration lower than the first impurity concentration;
- a first transistor including a channel region formed in said second surface portion of said well region;
- and
- a second transistor having a channel region formed in said second surface portion of said well region,
- wherein said channel regions of said first and second transistors are offset relative to each other.
3 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a first well region of a first conductivity type formed in said semiconductor substrate, said first well region including a first portion of the first conductivity type having a first surface impurity concentration;
- a second well region of the first conductivity type formed in said semiconductor substrate, said second well region including a second portion of the first conductivity type having a second surface impurity concentration lower than the first surface impurity concentration of said first portion of said first well region, said second well region including a shallow portion, corresponding to said second portion, which is shallower than said first well region;
- a first insulated-gate field-effect transistor formed in said first well region and having a channel region formed in said first portion of said first well region;
- and
- a second insulated-gate field-effect transistor formed in said second well region and having a channel region formed in said second portion of said second well region,
- wherein the impurity concentration of said second portion increases toward said second well region from said channel region of said second insulated-gate field-effect transistor along a lateral direction and decreases toward said semiconductor substrate from said channel region of said second insulated-gate field-effect transistor along a vertical direction.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a first well region of a first conductivity type formed in said semiconductor substrate, said first well region including a first portion of the first conductivity type having a first surface impurity concentration;
- a second well region of the first conductivity type formed in said semiconductor substrate, said second well region including a second portion of the first conductivity type having a second surface impurity concentration lower than the first surface impurity concentration of said first portion of said first well region, said second well region including a shallow portion, corresponding to said second portion, which is shallower than said first well region;
- a first insulated-gate field-effect transistor formed in said first well region and having a channel region formed in said first portion of said first well region;
- and
- a second insulated-gate field-effect transistor formed in said second well region and having a channel region formed in said second portion of said second well region,
- wherein a width of said channel region of said first insulated-gate field-effect transistor is greater than a width of said channel region of said second insulated-gate field-effect transistor.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a first well region of a first conductivity type formed in said semiconductor substrate, said first well region including a first portion of the first conductivity type having a first surface impurity concentration;
- a second well region of the first conductivity type formed in said semiconductor substrate, said second well region including a second portion of the first conductivity type having a second surface impurity concentration lower than the first surface impurity concentration of said first portion of said first well region said second well region including a shallow portion, corresponding to said second portion, which is shallower than said first well region;
- a first insulated-gate field-effect transistor formed in said first well region and having a channel region formed in said first portion of said first well region;
- a second insulated-gate field-effect transistor formed in said second well region and having a channel region formed in said second portion of said second well region;
- and
- a third insulated-gate field-effect transistor formed in said second well region and having a channel region formed in said second portion of said second well region, wherein said channel region of said third insulated-gate field-effect transistor and said channel region of said second insulated-gate field effect transistor are aligned.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- a first well region of a first conductivity type formed in said semiconductor substrate, said first well region including a first portion of the first conductivity type having a first surface impurity concentration;
- a second well region of the first conductivity type formed in said semiconductor substrate, said second well region including a second portion of the first conductivity type having a second surface impurity concentration lower than the first surface impurity concentration of said first portion of said first well region, said second well region including a shallow portion, corresponding to said second portion, which is shallower than said first well region;
- a first insulated-gate field-effect transistor formed in said first well region and having a channel region formed in said first portion of said first well region;
- a second insulated-gate field-effect transistor formed in said second well region and having a channel region formed in said second portion of said second well region;
- and
- a third insulated-gate field-effect transistor formed in said second well region and having a channel region formed in said second portion of said second well region, wherein said channel region of said third insulated-gate field-effect transistor and said channel region of said second insulated-gate field effect transistor are offset relative to each other.
4 more elements
Dependencies are inferred from the claim text.