Single-instruction-multiple-data processing using multiple banks of vector registers
AssigneeSamsung Electronics Co., Ltd.
InventorsLe Trong Nguyen, Seungyoon Peter Song, Moataz A. Mohamed, Heonchul Park, Roney Sau Don Wong
Life of this patent
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Abstract
A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.
Claims13
A vector processor comprising:
- a first bank of vector registers, wherein each vector register numbers assigned to other vector registers in the first bank;
- a second bank of vector registers, wherein each vector register in the second bank is assigned a register number which is distinct from register numbers assigned to other vector registers in the second bank but is the same as a register number assigned to a corresponding vector register in the first bank;
- a control register which includes a first field, the first field storing a value that identifies one of the first and second banks as a default bank;
- and
- selection circuitry for first and second banks of vector registers, wherein the selection circuitry is operable in a first mode to access a vector register that is in the default bank and is identified by a register number from an instruction being executed by the vector processor.
A method for operation a vector processor, comprising:
- assigning register numbers to vector registers in a first bank, wherein for each vector register in the first bank the assigned register number is distinct from register numbers assigned to other vector registers in the first bank;
- assigning register numbers to vector registers in a second bank, wherein for each vector register in the second bank the assigned register number is distinct from register numbers assigned to other vector registers in the second bank and is the same as a register number assigned to a corresponding vector register in the first bank;
- and
- executing a first instruction that includes a register number, wherein executing the instruction includes accessing a vector register that is assigned the register number included in the first instruction and is in a bank indicated by a field of a control register of the vector processor.
Dependencies are inferred from the claim text.