Method and apparatus for extracting an embedded clock from a digital data signal

A method for conducting digital data communications between a transmit site and a receive site comprising the steps of:

• at said transmit site,
• (a) encoding a serial digital bit stream by interleaving respective ones of complementary pairs of overhead bits between successive groups of data bits of said serial digital bit stream, scrambling the resulting encoded serial digital bit stream, and transmitting the scrambled digital bit stream to said receive site;
• and,
• at said receive site,
• (b) receiving the scrambled digital bit stream transmitted from said transmit site in step (a);
• (c) extracting, from said received scrambled digital bit stream, an embedded clock signal therein that falls within a data clock signal range, by
• (c1) deriving, from said received scrambled digital bit stream, a data rate estimate signal representative of an estimate of the data rate of data contained in said received scrambled digital bit stream, to within a prescribed range of frequency uncertainty,
• (c2) generating, in accordance with said data rate estimate signal derived in step (c)(1), a first precision reference clock signal that is variable over a first reference clock frequency range, less than said data clock signal range,
• (c3) applying said first precision reference clock signal to a first tunable phase lock loop circuit, having a first loop acquisition range corresponding to said first reference clock frequency range, said first tunable phase lock loop circuit generating a variable data rate synchronization clock signal that is a selectable multiple of said first precision reference clock signal, said variable data rate synchronization clock signal being variable over a second clock frequency range proximate to said data clock signal range, and
• (c4) applying said received scrambled digital bit stream and said variable data rate synchronization clock signal to a second tunable phase lock loop circuit, having a second loop acquisition range corresponding to said second clock frequency range, said second tunable phase lock loop circuit varying the frequency of said first precision reference clock signal over a third frequency range that encompasses said prescribed range of frequency uncertainty, until said variable data rate synchronization clock signal generated by said first tunable phase lock loop circuit coincides with said embedded clock signal;
• (d) descrambling said scrambled serial digital bit stream using said variable data rate synchronization clock signal;
• and
• (e) decoding the serial digital bit stream descrambled in step (d) to extract said groups of data bits exclusive of said complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of said data bits.

An apparatus for deriving, from a digital data signal, an embedded clock signal that falls within a data clock signal range comprising:

• a data rate estimator which derives, from said digital data signal, a data rate estimate signal representative of an estimate of the data rate of data contained in said digital data signal, to within a prescribed range of frequency uncertainty;
• a direct digital synthesizer which, in response to said data rate estimate signal derived by said data rate estimator, generates a first precision reference clock signal that is variable over a first reference clock frequency range, less than said data clock signal range;
• a first tunable phase lock loop circuit, to which said first precision reference clock signal is applied, said first tunable phase lock loop circuit having a first loop acquisition range corresponding to said first reference clock frequency range, and being operative to generate a variable data rate synchronization clock signal that is a selectable multiple of said first precision reference clock signal, said variable data rate synchronization clock signal being variable over a second clock frequency range proximate to said data clock signal range;
• and
• a second tunable phase lock loop circuit, to which said digital data signal and said variable data rate synchronization clock signal are applied, said second tunable phase lock loop circuit having a second loop acquisition range corresponding to said second clock frequency range, and being operative to vary the frequency of said first precision reference clock signal over a third frequency range that encompasses said prescribed range of frequency uncertainty, until said variable data rate synchronization clock signal generated by said first tunable phase lock loop circuit coincides with said embedded clock signal.

A system for conducting digital data communications between a transmit site and a receive site comprising:

• at said transmit site,
• a pre-scramble encoder which encodes a serial digital bit stream by interleaving respective ones of complementary pairs of overhead bits between successive groups of data bits of said serial digital bit stream;
• a scrambler which scrambles the encoded serial digital bit stream encoded by said pre-scrambled encoder;
• and
• a transmitter which transmits the scrambled encoded digital bit stream to said receive site;
• at said receive site,
• a receiver which receives the scrambled encoded digital bit stream transmitted from said transmit site;
• a variable bit synchronizer which extracts, from said received scrambled encoded digital bit stream, an embedded clock signal therein that falls within a data clock signal range, said variable bit synchronizer including
• a data rate estimator which derives, from said received scrambled encoded digital bit stream, a data rate estimate signal representative of an estimate of the data rate of data contained in said received scrambled encoded digital bit stream, to within a prescribed range of frequency uncertainty,
• a direct digital synthesizer which, in response to said data rate estimate signal derived by said data rate estimator, generates a first precision reference clock signal that is variable over a first reference clock frequency range, less than said data clock signal range,
• a first tunable phase lock loop circuit, to which said first precision reference clock signal is applied, having a first loop acquisition range corresponding to said first reference clock frequency range, and generating a variable data rate synchronization clock signal that is a selectable multiple of said first precision reference clock signal, said variable data rate synchronization clock signal being variable over a second clock frequency range proximate to said data clock signal range, and
• a second tunable phase lock loop circuit, to which said received scrambled digital bit stream and said variable data rate synchronization clock signal are applied, said second tunable phase lock loop circuit having a second loop acquisition range corresponding to said second clock frequency range, and being operative to vary the frequency of said first precision reference clock signal over a third frequency range that encompasses said prescribed range of frequency uncertainty, until said variable data rate synchronization clock signal generated by said first tunable phase lock loop circuit coincides with said embedded clock signal;
• a descrambler which descrambles said scrambled encoded serial digital bit stream using said variable data rate synchronization clock signal;
• and
• a decoder which decodes the descrambled serial digital bit stream to extract said groups of data bits exclusive of said complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of said data bits.

A data and clock recovery arrangement for use with a system for conducting digital data communications between a transmit site and a receive site, which includes, at said transmit site, a pre-scramble encoder which encodes a serial digital bit stream by interleaving respective ones of complementary pairs of overhead bits between successive groups of data bits of said serial digital bit stream, a scrambler which scrambles the encoded serial digital bit stream encoded by said pre-scrambled encoder, and a transmitter which transmits the scrambled encoded digital bit stream to said receive site and, at said receive site, a receiver which receives the scrambled encoded digital bit stream transmitted from said transmit site, said data and clock recovery arrangement comprising:

• a data rate independent variable bit synchronizer which extracts, from said received scrambled encoded digital bit stream, an embedded clock signal therein that falls within a data clock signal range, said data rate independent variable bit synchronizer being capable of accepting any data rate within said data clock signal range, and being operative to automatically tune itself to the data clock signal embedded in the received scrambled encoded serial data stream, and outputting respective scrambled encoded serial data and clock signals;
• a descrambler which descrambles said scrambled encoded serial digital bit stream in dependence upon said variable data rate synchronization clock signal;
• and
• a decoder which decodes the descrambled serial digital bit stream to extract said groups of data bits exclusive of said complementary pairs of overhead bits and to derive an output clock signal having a frequency coincident with the data rate of said data bits.

A method for recovering a clock signal embedded in a digital bit stream, said embedded clock signal being capable of being any frequency within a prescribed frequency range of variation, comprising the steps of:

• (a) processing said digital bit stream to identify an octave within said prescribed frequency range containing said embedded clock and deriving a code representative of an estimate of the frequency of said embedded clock signal within the identified octave, which frequency estimate is within a prescribed frequency uncertainty about said embedded clock frequency;
• (b) setting the output frequency of a highly precise reference clock generator having a single octave of tuning range to a frequency value, which, when multiplied by a scaling factor determined in accordance with said code, produces a scaled frequency corresponding to said frequency estimate;
• and
• (c) adjusting the value of said code by means of a phase locked loop, to which said scaled frequency signal and said digital bit stream are applied, through a vernier frequency range that encompasses said prescribed frequency uncertainty, until the output frequency of said highly precise reference clock generator, when multiplied by said scaling factor, corresponds to the frequency of said embedded clock.

A method for extracting, from a digital data signal, an embedded clock signal that falls within a data clock signal range comprising the steps of:

• (a) monitoring said digital data signal and deriving therefrom a data rate estimate signal representative of an estimate of the data rate of data contained in said digital data signal;
• (b) generating a reference clock signal having a frequency established in accordance with said data rate estimate signal;
• (c) coupling said reference clock signal generated in step (b) to a first input of a phase detector having a second input coupled to receive said digital data signal, and an output;
• (d) providing a sweepable loop filter in a loop path including said reference clock signal and said phase detector, thereby forming a phase-locked loop;
• and
• (e) controllably sweeping said loop filter, and thereby said phase-locked loop, until said phase detector produces an output representative that said phase-locked loop is locked to said embedded clock signal of said digital data signal.

An apparatus for extracting, from a digital data signal, an embedded clock signal that falls within a data clock signal range comprising:

• a data rate estimator coupled to receive said digital data signal and being operative to derive therefrom a data rate estimate signal representative of an estimate of the data rate of data contained in said digital data signal;
• a phase-locked loop that includes a reference clock signal generator, a phase detector having a first input coupled to receive said digital data signal, a second input coupled to receive a signal representative of said reference clock signal, and an output, and a sweepable loop filter coupled in a loop path including said reference clock signal generator and said phase detector;
• and
• a controller which is operative to establish said reference clock signal generated by said reference clock signal generator in accordance with said data rate estimate signal, and to thereafter controllably sweep said loop filter, and thereby said phase-locked loop, until said phase detector produces an output representative that said phase-locked loop is locked to said embedded clock signal of said digital data signal.