# US 5,838,040 A · Nonvolatile reprogrammable interconnect cell with FN tunneling in sense

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- Number: US 5,838,040 A
- Document ID: US5838040A
- Status: Granted
- Kind: A
- Application number: 08/829,374
- Filed: 1997-03-31
- Granted: 1998-11-17
- Earliest claimed: 1997-03-31
- Assignees: GateField Corporation
- Inventors: Robert M. Salter, III; Kyung Joon Han; Jack Zezhong Peng; Victor Levchenko; Robert V. Broze
- Web page: https://patentgrep.com/patent/US5838040A

## CPC

- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.

## Claims

### Claim 1

A programmable interconnect for selectively connecting circuit nodes in an integrated circuit comprising
a first field effect transistor having first and second source/drains connected to a first and a second circuit node, a floating gate for storing charge, and a control gate for turning said first field effect transistor on and off responsive to charge on the floating gate,
a second field effect transistor having first and second source/drains, a floating gate separated from at least one source/drain by tunneling dioxide, and a control gate capacitively coupled to the floating gate, the floating gate of the first and second field effect transistors being interconnected, and
a first conductive line and a second conductive line connected to the first and second source/drains of the second field effect transistor, whereby programming of the interconnect is effected by applying voltages to the first and second conductive lines and to the control gate of the second field effect transistor, and the sensing of conducting and non-conducting states of a node is by selectively monitoring conduction of the second field effect transistor through the first conductive line and the second conductive line.

### Claim 2 (depends on 1)

The programmable interconnect as defined by claim 1 wherein said floating gates comprise a first polysilicon line running between and spaced from the source/drains of the first field effect transistor and running between and spaced from the source/drains of the second field effect transistor.

### Claim 3 (depends on 2)

The programmable interconnect as defined by claim 2 wherein said control gates comprise a second polysilicon line extending to adjacent programmable interconnects in an array of programmable interconnects.

### Claim 4 (depends on 3)

The programmable interconnect as defined by claim 3 wherein the first and second conductive lines comprise metal lines running perpendicular to the first polysilicon line and the second polysilicon line.

### Claim 5 (depends on 4)

The programmable interconnect as defined claim 4 wherein the first polysilicon line is restricted to the first field effect transistor and the second field effect transistor.

### Claim 6 (depends on 5)

A programmable interconnect as defined by claim 5 wherein the first polysilicon line and the second polysilicon line are self-aligned.

### Claim 7 (depends on 6)

The programmable interconnect as defined by claim 6 wherein the first field effect transistor is formed in a first region of a semiconductor body, the second field effect transistor is formed in a second region of the semiconductor body adjacent to the first region.

### Claim 8

An array of programmable interconnects for selectively connecting circuit nodes in an integrated circuit comprising
a plurality of interconnect cells arranged in rows and columns and each programmable to connect and disconnect circuit nodes,
each cell having a first field effect transistor aligned with first field effect transistors of cells in a first column, and a second field effect transistor aligned with second field effect transistors of cells in a second column, the first and second field effect transistors of a cell being aligned with first and second field effect transistors of cells in the same row,
each cell having a first polysilicon line running between and spaced from source/drains of the first field effect transistor and between and spaced from source/drains of the second field effect transistor and functioning as a common floating gate for the first and second field effect transistors, a second polysilicon line overlying the first polysilicon line and functioning as a common control gate for the first and second field effect transistors, the second polysilicon line extending to other cells in a row, and first and second metal lines contacting source/drains of the second field effect transistor and extending to other cells in a column, whereby programming of a cell is effected by applying voltages to the first and second metal lines and to the second polysilicon line, and the sensing of conducting and nonconducting states of a node is by selectively monitoring conductance of the second field transistor of the cell through the first and second metal lines.