Etching method for extending i-line photolithography to 0.25 micron linewidth

Abstract

A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereupon a blanket target layer. Formed upon the blanket target layer is a blanket focusing layer, where the blanket focusing layer is formed from an organic material and where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in etching the blanket focusing layer to form a patterned focusing layer. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer. There is then etched through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer. The patterned focusing layer so formed has the reproducible negative etch bias with respect to the patterned photoresist layer. Finally, the blanket target layer is etched through a second etch method to form a patterned target layer while employing the patterned focusing layer as a second etch mask layer. When: (1) the patterned photoresist layer has a linewidth dimension about 0.33 to about 0.35 microns; (2) the reproducible negative etch bias is from about -0.07 to about -0.09 microns; and (3) the second etch method does not have a reproducible second etch bias which substantially compensates the reproducible negative etch, a patterned target layer, such as a gate electrode within a field effect transistor (FET), of linewidth dimension as narrow as about 0.25 microns may be obtained.

Dependencies are inferred from the claim text.