SRAM having load transistor formed above driver transistor

A semiconductor integrated circuit device comprising:

• a semiconductor substrate having a main surface;
• a first semiconductor region of p type conductivity formed, at a first region on said main surface, in said semiconductor substrate;
• a second semiconductor region of n type conductivity formed in said semiconductor substrate, wherein said first semiconductor region is formed in said second semiconductor region;
• a third semiconductor region of p type conductivity formed in said semiconductor substrate;
• memory cells formed at a second region on said main surface of said semiconductor substrate and formed on said third semiconductor region, each of said memory cells including an n-channel driver MISFET and a p channel load MISFET, wherein each of said load MISFETs has a source region, a drain region, and a channel forming region formed in a semiconductor strip;
• a first insulating film formed over said driver MISFETs and said first semiconductor region so as to cover said first and said second region, wherein said load MISFETs and said semiconductor strips are formed over said first insulating film;
• a first wiring line, formed over said first insulating film and integrally formed with said source regions of said load MISFETs of said memory cells, for supplying a first voltage to said memory cells, wherein said source regions of said load MISFET and said first wiring line have p type conductivity;
• a second insulating film formed over said load MISFETs and said first insulating film so as to cover said first and said second region;
• and
• a second wiring line, formed over said second insulating film, for supplying said first voltage to said first wiring line,
• wherein resistance of said second wiring is lower than resistance of said first wiring,
• wherein said first wiring line extends over said first and said second region and is electrically connected to said first semiconductor region through a first opening which is formed in said first insulating film,
• wherein said second wiring line is formed over said first region and is electrically connected to said first semiconductor region through a second opening which is formed in both said first insulating film and said second insulating film, and
• wherein said first opening and said second opening are separately positioned each other within said first region, such that said first semiconductor region serves to connect the first wiring line and the second wiring line to one another between the first and second openings so that said second wiring line can supply the first voltage to the first wiring line.

A semiconductor memory device comprising:

• a semiconductor substrate having a main surface;
• a first semiconductor region of a first conductivity type formed, at a first region of said main surface, in said semiconductor substrate;
• memory cells formed at a second region of said main surface and each including a first MISFET and a second MISFET,
• wherein a source region and a drain region of said MISFET are formed in said semiconductor substrate and have a second conductivity type opposite to said first conductivity type,
• wherein a gate electrode of said first MISFET is formed over said main surface,
• wherein a gate insulating film of said first MISFET is formed between said gate electrode thereof and said main surface;
• a first insulating film formed over said gate electrodes of said first MISFETs and said first semiconductor region so as to cover said first and said second region,
• wherein each of said second MISFETs has a source region and a drain region formed in a semiconductor strip,
• wherein said second MISFETs and said semiconductor strips are formed over said first insulating film;
• a first wiring line formed over said first insulating film and electrically coupled to said source regions of said second MISFETs of said memory cells,
• wherein said first wiring line is comprised of said semiconductor material having the same conductivity type as said source regions of said second MISFETs and said first semiconductor region,
• a second insulating film formed over said second MISFETs and said first insulating film so as to cover said first and second region;
• and
• a second wiring line formed over said second insulating film,
• wherein resistance of said second wiring is lower than that of said first wiring,
• wherein said first wiring line extends over said first and said second region and is electrically connected to said first semiconductor region through a first opening which is formed in said first insulating film,
• wherein said second wiring line is formed over said first region and is electrically connected to said first semiconductor region through a second opening which is formed in both said first insulating film and said second insulating film,
• wherein said first opening and said second opening are formed within said first region such that said first semiconductor region serves to contact said first wiring line and said second wiring line to one another through said first opening and said second opening,
• wherein a predetermined potential is supplied from said second wiring line to said source regions of said second MISFET through said first semiconductor region and said first wiring line.