Apparatus for testing a controller with random contraints

A system for testing an IDE controller comprising:

• an IDE controller module for simulating the IDE controller, wherein the IDE controller includes primary and secondary channels and a host interface;
• a primary control module for generating primary data patterns and for transmitting and receiving the primary data patterns via the host interface and the primary channel;
• a secondary control module for generating secondary data patterns and for transmitting and receiving the secondary data patterns via the host interface and the secondary channel;
• a primary device module, coupled to the primary channel, for receiving the primary data patterns transmitted from the primary control module and transmitting the primary data patterns back to a primary verification module via the primary channel, wherein the primary verification module determines whether the primary data patterns match expected values;
• a secondary device module, coupled to the secondary channel for receiving the secondary data patterns transmitted from the secondary control module and transmitting the secondary data patterns back to a secondary verification module via the secondary channel, wherein the secondary verification module determines whether the secondary data patterns match expected values;
• and
• a host request module for arbitrating access to the host interface between the primary and secondary control modules.

A system for testing an IDE controller comprising:

• an IDE controller module for simulating the IDE controller, wherein the IDE controller includes primary and secondary channels and a host interface;
• a primary control module, coupled to the host interface, for testing the primary channel;
• a secondary control module, coupled to the host interface for testing the secondary channel;
• and
• a host request module for arbitrating access to the host interface between the primary and secondary control modules;
• wherein the primary control module executes a primary test procedure that generates random primary test constraints and primary data patterns and programs the IDE controller with the random primary test constraints such that the primary data patterns are communicated through the IDE controller via the primary channel in accordance with the random primary test constraints;
• and
• wherein the secondary control module executes a secondary test procedure that generates random secondary test constraints and secondary data patterns and programs the IDE controller with the random secondary test constraints such that the secondary data patterns are communicated through the IDE controller via the secondary channel in accordance with the random secondary test constraints.

A test bench simulation environment for testing a controller design, comprising:

• means for providing a controller model having a primary and a secondary channel and a host interface;
• means for providing a primary device model coupled to the primary channel;
• means for providing a secondary device model coupled to the secondary channel;
• means for transmitting data patterns to the primary and secondary device models, wherein the transmission of the data patterns is performed across the host interface;
• means for receiving data patterns from the primary and secondary device models and determining whether the data patterns match expected values, wherein the data patterns are transmitted from the primary and secondary device models across the host interface;
• and
• means for arbitrating the transmission of the data patterns across the host interface.