Shared memory fabric architecture for very high speed ATM switches
AssigneeLSI Logic Corporation
InventorsSubir Varma, Thomas Daniel
Life of this patent
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Abstract
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches including a multi-dimensional array of electrically interconnected N*M switch modules, where N>>M. The fabric architecture also includes input ports for providing cells to the array of switch modules. The input ports operate at a predetermined speed S. The fabric architecture additionally includes memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module. The memory devices include on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y<<N.
Claims15
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the fabric architecture comprising:
- a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M;
- a plurality of input ports for providing cells to said array of switch modules, said input ports being characterized by a predetermined speed S;
- and
- a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each of said switch modules, the plurality of memory devices including a plurality of on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and a plurality of off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y is less than N.
A shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the fabric architecture comprising:
- a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M, said switch modules being adapted to support per-VC queuing;
- a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each switch module;
- and
- an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
A chip set including a distributed shared memory switch architecture, the chip set including:
- a plurality of electrically interconnected integrated circuit modules including:
- a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M, said switch models being adapted to support per-VC queuing;
- a plurality of memory devices electrically connected to said array to provide a hierarchical memory structure at each switch module;
- and
- an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
A method of manufacturing a shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the method comprising the steps of:
- (a) providing a plurality of switch modules, said switch modules being adapted to support per-VC queuing;
- (b) electrically interconnecting the switch modules as a N*M two-dimensional array, where N is greater than M;
- (c) providing a plurality of memory devices;
- (d) electrically connecting the memory devices to the array to provide a hierarchical memory structure at each switch module;
- and
- (e) providing an output port controller embodying a scheduler adapted to implement a plurality of cell scheduling disciplines.
A method of manufacturing a shared memory fabric architecture for asynchronous transfer mode (ATM) switches, the method comprising the steps of:
- (a) providing a multi-dimensional array of electrically interconnected N*M switch modules, where N is greater than M;
- (b) providing a plurality of input ports for providing cells to the array of switch modules, the input ports being characterized by a predetermined speed S;
- and
- (c) providing a plurality of memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module, the plurality of memory devices including a plurality of on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and a plurality of off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S where Y is less than N.
Dependencies are inferred from the claim text.