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US 5,831,924 AGranted
Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYasuhiko Nitta, Masaki Tsukude
Life of this patent
Estimating the term…
Abstract
One memory array is divided into a plurality of banks sharing a row of memory cells. Global IO buses are disposed for memory column blocks forming the plurality of banks included in one memory array. The global IO buses are selectively and electrically connected to the same data input/output terminal.
Claims15
A synchronous semiconductor memory device operating in synchronization with a clock signal applied repetitively regardless of whether an access is made or not, comprising:
- at least one data terminal for at least one of input and output of an external data of at least 1 bit;
- and
- at least one memory array provided corresponding to said at least one data terminal, said memory array including a plurality of memory cells arranged in a matrix of rows and columns;
- said memory array being divided into a plurality of banks arranged adjacent to each other, aligned with respect to as row of said memory cells, and each bank being driven into an array activated state or an array inactivated state by a controller responsive to a bank designation signal, regardless of whether other banks each are in the activated state or in the inactivated state, a bank in said array activated state having a row of memory cells in said bank driven and held in a selected state.
1 more element
Dependencies are inferred from the claim text.