Low voltage digital-to-analog converter

An N-bit digital-to-analog converter (DAC) comprising:

• 2.sup.(N+1) -1 resistors coupled in series ranging from a resistor R(0) to a resistor R(2.sup.N+1 -2), thereby defining 2.sup.(N+1) -2 nodes between adjacent resistors ranging from N(0) to N(2.sup.N+1 -3), where resistor R(0) and resistor R(2.sup.N+1 -2) each have a free end node;
• a fixed output node at one of said nodes;
• 2.sup.N NMOS transistors ranging from MN(2.sup.N -1) to MN(0);
• a first voltage node coupled to said free end node of resistor R(0) by transistor MN(2.sup.N -1), and to nodes N(0) to N(2.sup.N -2) by transistors MN(2.sup.N -2) to MN(0), respectively;
• 2.sup.N PMOS transistors ranging from MP(2.sup.N -1) to MP(0);
• a second voltage node that is positive relative to said first voltage node, said second voltage node being coupled to nodes N(2.sup.N -1) to N(2.sup.N+1 -3) by transistors MP(2.sup.N -1) to MP(1) respectively, and to said free end node of resistor R(2.sup.N+1 -2) by transistor MP(0);
• a decoder coupled to and capable of switching on and switching off said NMOS transistors and said PMOS transistors, said decoder having a digital input N bits wide, where for a digital input representing the value X, transistors MN(X) and MP(X) are switched on.

A method for digital-to-analog conversion using a series connection of resistors, said series having a first end and a second end, a node being defined between each of a plurality of resistor pairs of said series, a node also being defined at said first and said second end of said series of resistors, a fixed node being located between said first end and said second end inclusive, a first plurality of switches arranged to be able to apply a first voltage to a first set of nodes adjacent to said first end, a second plurality of switches arranged to be able to apply a second voltage to a second set of nodes adjacent to said second end, said method comprising the steps of:

• closing at least one switch of said first plurality of switches to apply said first voltage to a first node of said series connection of resistors;
• closing at least one switch of second plurality of switches to apply said second voltage to a second node of said series connection of resistors;
• and
• deriving an output voltage at an output from said fixed node between said first node and said second node, said output being essentially always equip potential with said fixed node.

A method for providing digital-to-analog conversion comprising:

• providing 2.sup.(N+1) -1 resistors coupled in series ranging from a resistor R(0) to a resistor R(2.sup.N+1 -2), thereby defining 2.sup.(N+1) -2 nodes between adjacent resistors ranging from N(0) to N(2.sup.N+1 -3), where resistor R(0) and resistor R(2.sup.N+1 -2) each have a free end node;
• providing a fixed output node at one of said nodes;
• providing 2.sup.N NMOS transistors ranging from MN(2.sup.N -1) to MN(0);
• coupling a first voltage node to said free end node of resistor R(0) by transistor MN(2.sup.N -1), and to nodes N(0) to N(2.sup.N -2) by transistors MN(2.sup.N -2) to MN(0), respectively;
• providing 2.sup.N PMOS transistors ranging from MP(2.sup.N -1) to MP(0);
• coupling a second voltage node that is positive relative to said first voltage node to nodes N(2.sup.N -1) to N(2.sup.N+1 -3) by transistors MP(2.sup.N -1) to MP(1) respectively, and to said free end node of resistor R(2.sup.N+1 -2) by transistor MP(0);
• decoding a digital input representing the value X, said digital input being N bits wide;
• and
• switching on transistors MN(X) and MP(X).

A method for making a digital-to-analog converter comprising:

• forming a plurality of resistors connected in series on a semiconductor substrate, thereby defining a plurality of nodes between said plurality of resistors;
• permanently electrically coupling an output to a fixed node between a pair of said resistors;
• forming a plurality of switches on said semiconductor substrate that couple a voltage source to said plurality of nodes;
• and
• forming a decoder on said semiconductor substrate that is responsive to a digital input and which controls said plurality of switches such that an analog voltage corresponding to said digital input is developed at said output.

A digital-to-analog converter comprising:

• an N bit input representing a value X, said N bit input having M most significant bits and L least significant bits, where N is equal to M plus L;
• a first LSB bank of LSB resistors coupled in series with a first MSB bank of MSB resistors, said first LSB bank and said first MSB bank being coupled between a first voltage node and a fixed output node;
• a second LSB bank of LSB resistors coupled in series with a second MSB bank of MSB resistors, said second LSB bank and said second MSB bank being coupled between a second voltage node and said fixed output node;
• an MSB decoder coupled to said N bit input to decode the most significant M bits of said input, said MSB decoder controlling said first MSB bank and said second MSB bank;
• an LSB decoder coupled to said N bit input to decode the least significant L bits of said input, said LSB decoder controlling said first LSB bank and said second LSB bank, whereby said LSB decoder operates to selectively apply said first voltage to said first LSB bank, and said second voltage to said second LSB bank, and said MSB decoder operates to selectively apply a first LSB output from said first LSB bank to said first MSB bank and operates to selectively apply a second LSB output from said second LSB bank to said second MSB bank.