Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port

An apparatus for performing read and write operations to an embedded memory of an integrated circuit, the integrated circuit including a CPU one or more internal registers, and a memory interface unit with an access circuitry which provides access to the embedded memory via the memory interface unit without use of the CPU, the internal registers coupled to the memory interface unit for reading and writing memory locations of the embedded memory, the apparatus comprising:

• an input/output (I/O) means coupled between an external host and the integrated circuit for transmission of signals between the external host and a selected internal register of the integrated circuit, the I/O means comprising a register coupled between the external host and the selected internal register for transmitting said signals comprising addresses, data and instructions from the external host to the selected internal register,
• an I/O controller coupled to the external host and the selected internal register for transmitting signals comprising controls from the external host to the selected internal register, the I/O controller further coupled to the register for receiving signals comprising instructions transmitted from the external host to the register, and
• an output connection coupled between the selected internal register and the external host for transmitting signals comprising addresses, data and instructions from the selected internal register to the external host.

A method for testing an embedded memory of an integrated circuit, the method comprising the steps of:

• instructing the integrated circuit to execute a preselected operation using a first set of data;
• storing in the embedded memory a second set of data produced by execution of the preselected operation in the integrated circuit;
• and
• reading the second set of data from the embedded memory by means of
• transmitting a memory access instruction from an external host to a register of an input/output (I/O) means within the integrated circuit, the I/O means further comprising an output connection coupled to the external host, and an I/O controller;
• the I/O controller acquiring control over a memory bus within the integrated circuit in response to execution of the memory access instruction;
• transmitting signals from the external host via the register to a memory shift register within the integrated circuit, the memory shift register coupled to an access circuitry of a memory interface unit within the intergrated circuit for enabling access to the embedded memory without use of the central processing unit of the integrated circuit, the signals comprising at least an address specifying a memory location within the embedded memory and an instruction specifying a read operation from the specified memory location, and
• transmitting the address, and the data stored in the specified memory location to the external host via the output connection;
• and
• comparing the second set of data with a predetermined result.

A method of accessing an embedded memory of an integrated circuit, the method comprising the steps of:

• an external host transmitting a memory access instruction to a test access port within the integrated circuit, the test access port coupled to the external host and including an input/output (I/O) controller;
• the I/O controller acquiring control over a memory bus within the integrated circuit in response to execution of the memory access instruction;
• the external host transmitting data via the test access port to a memory access register within the integrated circuit, the memory access register coupled to a memory access circuitry within the the intergrated circuit enabling access to memory locations of the embedded memory without use of the central processing unit of the integrated circuit, the data comprising an address specifying a memory location within the embedded memory, and an access operation;
• and
• the memory access circuitry accessing the memory location specified by performing the access operation.

An apparatus for accessing an embedded memory of an integrated circuit, the apparatus comprising:

• a test access port coupled between an external host and a memory interface unit (MIU) of the integrated circuit, the test access port transmitting signals between the external host and the MIU, the test access port including an instruction register configured to transmit a signal from the external host to the MIU, the signal comprising an address, data and a command,
• an input/output (I/O) controller coupled to the external host and the MIU, the I/O controller providing control signals to the MIU from the external host, and
• an output connection coupled between the external host and the MIU, the output connection outputting data retrieved from the embedded memory through the MIU to the external host;
• and
• a register internal to the MIU, the register coupled to an access circuitry of the MIU, the access circuitry providing access to the embedded memory responsive to the command.