US 5,828,578 AGranted

Microprocessor with a large cache shared by redundant CPUs for increasing manufacturing yield

AssigneeS3 Incorporated

InventorJames S. Blomgren

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Abstract

Manufacturing yield is increased and cost lowered when a second, substantially identical CPU core is placed on a microprocessor die when the die contains a large cache. The large cache is shared among the two CPU cores. When one CPU core is defective, the large cache memory may be used by the other CPU core. Thus having two complete CPU cores on the die greatly increases the probability that the large cache can be used, and the manufacturing yield is therefore increased. When both CPU cores are functional, the die may be sold as a dual-processor. However, when no dual-processor chips are to be sold, the die are still manufactured as dual-processor die but packaged only as uni-processor chips. With the higher total yield of the dual-CPU die, the dual-CPU die may be packaged solely as uni-processor chips at lower cost than using uni-processor die. An on-chip ROM for generating test vectors, a floating point unit, and a bus-interface unit are also shared along with the large cache.

Claims13

Dependent claims

A method of manufacturing microprocessors comprising:

fabricating on a wafer a plurality of dual-processor die, each dual-processor die having a first CPU core, a second CPU core, a shared memory, and a plurality of bonding pads;
(a) making temporary electrical contact with the plurality of bonding pads on a first die (b)
(b) determining whether the shared memory contains a defect be applying a first set of stimuli to the plurality of bonding pads on the first die;
(c) upon a determination that the shared memory contains a defect, marking the first die as defective;
(d) determining whether the first CPU core contains a defect by applying a second set of stimuli to the plurality of bonding pads on the first die;
(e) determining whether the second CPU core contains a defect by applying a third set of stimuli to the plurality of bonding pads on the first die;
(f) upon determinations that the first CPU core contains a defect and that the second CPU core contains a defect, marking the first die as defective;
(g) upon determinations that the shared memory does not contain a defect and that the first CPU core does not contain a defect, marking the first die with a first functional marking;
(h) upon determinations that the shared memory does not contain a defect and that the second CPU core does not contain a defect, marking the first die with a second functional marking;
and
removing the temporary electrical contact with the first die and successively repeating steps (a) through (h) for each of the other dual-processor die.

8 more elements

An apparatus for manufacturing a microprocessor comprising;

a first processor core on a microprocessor die for executing general-purpose programs comprising instructions from an instruction set;
a second processor core on the microprocessor die for executing general-purpose programs comprising instructions from the instruction set, the second processor core substantially identical in function and capability to the first processor core;
a shared memory on the microprocessor dies coupled to the first processor core and coupled to the second processor core, for supplying instructions, to the first processor core and for supplying instructions to the second processor core;
bonding pads on the microprocessor die for connecting the shared memory to external devices, the first processor core and the second processor core accessing external devices through the shared memory and the bonding pads;
and
a marking on the microprocessor die for indicating the level of functionality of the first processor core, the second processor core and the shared memory;
wherein the marking is selected from the group consisting of a first defect marking indicating that the shared memory contains a defect, a second defect marking indicating that the first processor core contains a defect and that the second processor core contains a defect, a first functional marking indicating that the shared memory does not contain a defect and that the first processor core does not contain a defect, and a second functional marking indicating that the shared memory does not contain a defect and that the second processor core does not contain a defect,
whereby the first processor core and the second processor core are each for executing the general-purpose programs by receiving instructions from the shared memory.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/564,721Filed 29 Nov 1995
Granted: 27 Oct 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 11/2242
To test CPU or processors: in multi-processor systems, e.g. one processor becoming the primary tester
G01R 31/318566
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: comparators; Diagnosing the device under test
G06F 11/1641
Error detection by comparing the output of redundant processing systems: where the comparison is not performed by the redundant processing components
G06F 11/277
Tester hardware, i.e. output processing circuits: with comparison between actual response and known fault-free response