Multi-level conduction structure for VLSI circuits
AssigneeUnited Microelectronics Corp.
InventorsWater Lur, Jiunn Yuan Wu
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Abstract
This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.
Claims14
A multi-level conductor structure for VLSI circuits, comprising:
- a silicon substrate with circuits formed therein;
- a base dielectric layer formed on said silicon substrate;
- layers of electrodes having a first layer of electrodes and higher layers of electrodes;
- contact studs formed in said base dielectric layer forming electrical connections between said circuits in said silicon substrate and said first layer of electrodes;
- a multi-level structure comprising said layers of electrodes and inter-level studs wherein said inter-level studs form electrical connections between said layers of electrodes;
- a thin envelope oxide coating surrounding said electrodes and said inter-level studs;
- and
- a layer of passivation material with poor step coverage entirely covering said multi-level structure including said layers of electrodes and said air dielectric between said layers of electrodes.
Dependencies are inferred from the claim text.