US 5,827,776 A · Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Abstract

A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

Claims14

Dependent claims

A method for forming a multilevel interconnect structure, comprising:

forming at least two first conductors spaced across a semiconductor topography;
depositing a first dielectric upon said first conductors;
forming an etch stop upon a portion of said first dielectric;
depositing a second dielectric upon said etch stop;
etching through said second dielectric directly above said etch stop to form a trench while simultaneously etching through said second and first dielectrics directly above said first conductors to form a pair of vias;
filling said trench and said vias with a plug material;
and
forming at least two second conductors spaced across said second dielectric.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

08/959,106Filed 23 Oct 1997 · continuation

Priority

18 Jul 1996

Granted

27 Oct 1998

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/495
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes: capacitive…
H10W 20/01
Interconnections in chips, wafers or substrates: manufacture or treatment
H10W 20/089
By forming openings in the dielectric parts: using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Life of this patent

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Life of this patent

Abstract

Claims14