Compressed Instruction format for use in a VLIW processor
AssigneePhilips Electronics North America Corporation
InventorsEino Jacobs, Michael Ang
Life of this patent
Estimating the term…
Abstract
A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
Claims20
A computer storage medium comprising a stored VLIW instruction, which instruction comprises a plurality of operations for commencing execution in a same machine cycle on distinct functional units of a VLIW processor, each non-null operation being compressed according to a compression scheme which assigns a compressed operation length to that operation, the compressed operation length being chosen from a plurality of finite lengths, which finite lengths include at least two non-zero lengths, which of the finite lengths is chosen being dependent upon at least one feature of the operation.
The medium of 10 wherein the at least one field specifying the operation comprises at least one byte aligned sub-field.
The medium of 9 wherein the format field has 2*N bits, where N is the number of issue slots.
Dependencies are inferred from the claim text.