Method of processing multi-level signals for simple clock recovery
AssigneeNorthern Telecom Limited
InventorsMichael Altmann, Bernard Guay
Life of this patent
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Abstract
A method and a circuit for simple clock recovery from multi-level at high transmission rates. The circuit is compatible with standard PLL-type clock recovery techniques for NRZ and generalized two-level signalling. The timing information is extracted from a single threshold crossing, irrespective of the number of levels (M) of the signal. This was verified to provide sufficient spectral information for the proper operation of a clock recovery PLL. The threshold may be programmed for various line codes.
Claims8
A circuit for clock recovery from an M-ary signal, where M is the number of levels taken by said M-ary signal, comprising:
- a comparator for receiving said M-ary signal and one predetermined reference level and providing a two-level signal, said two-level signal assuming a first level whenever an amplitude of said M-ary signal is higher than said reference level and assuming a second level whenever the amplitude of said M-ary signal is lower than said reference level, such that said two-level signal comprises information on less than all transitions in said M-ary signal;
- a transition detector for receiving said two-level signal and providing a pseudo-clock signal;
- and
- a phase locked loop circuit for generating a recovered clock signal synchronized with said pseudo-clock signal.
A method for clock recovery from an M-ary signal, where M is the number of levels taken by said M-ary signal, comprising the steps:
- comparing said M-ary signal with one predetermined reference level to provide a two-level signal, said two-level signal assuming a first level whenever an amplitude of said M-ary signal is higher than said reference level and assuming a second level whenever the amplitude of said M-ary signal is lower than said reference level, such that said two-level signal comprises information on less than all transitions in said M-ary signal;
- generating a pseudo-clock signal comprising the transitions between said two levels in said two-level signal;
- and
- synchronizing a phase locked loop circuit with said pseudo-clock signal for generating a recovered clock signal.
Dependencies are inferred from the claim text.