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AssigneesCornell Research Foundation, Inc., Intel Corporation, Sematech, Inc.
InventorsYosef Schacham-Diamand, Valery M. Dubin, Chiu H. Ting, Bin Zhao, Prahalad K. Vasudev, Melvin Desilva
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A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.
A method of forming a protected catalytic seed surface in order to deposit metal by electroless deposition to form an interconnect structure on a semiconductor wafer, comprising the steps of:
In a fabrication of a semiconductor device, a method of forming a protected catalytic seed surface on a barrier metal in order to deposit metal by electroless deposition to form an interconnect structure on a semiconductor wafer, comprising the steps of:
In a formation of a semiconductor interconnect structure in which two conductive regions are separated by a dielectric layer and connected by said interconnect structure, a method of forming a protected catalytic seed surface on a barrier metal in order to deposit metal by electroless deposition to form an interconnect structure on a semiconductor wafer, comprising the steps of:
In a formation of a semiconductor interconnect structure in which two conductive regions are separated by a dielectric layer and connected by said interconnect structure, a method of forming a protected catalytic seed surface on a barrier metal in order to deposit metal by electroless deposition to form an interconnect structure on a semiconductor wafer, comprising the steps of:
Dependencies are inferred from the claim text.