Semiconductor integrated circuit for supplying a control signal to a plurality of object circuits

A semiconductor integrated circuit having:

• first and second delay controllers for receiving an input signal;
• a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• said real line from said first delay controller to said object circuits has a symmetrical tree shape;
• and
• a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object circuits.

A semiconductor integrated circuit having:

• first and second delay controllers for receiving an input signal;
• a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• said object circuits are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.

A semiconductor integrated circuit module having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• a length of said real line from said first delay controller to any one of said object semiconductor integrated circuits is substantially identical;
• and
• a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object semiconductor integrated circuits.

A semiconductor integrated circuit module having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• said real line from said first delay controller to said object semiconductor integrated circuits has a symmetrical tree shape;
• and
• a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object semiconductor integrated circuits.

A semiconductor integrated circuit module having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• said object semiconductor integrated circuits are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.

A semiconductor integrated circuit system having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• a length of said real line from said first delay controller to any one of said object semiconductor integrated circuit modules is substantially identical;
• and
• a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object semiconductor integrated circuit modules.

A semiconductor integrated circuit system having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• said real line from said first delay controller to said object semiconductor integrated circuit modules has a symmetrical tree shape;
• and
• a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object semiconductor integrated circuit modules.

A semiconductor integrated circuit system having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• said object semiconductor integrated circuit modules are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.

A semiconductor integrated circuit having:

• first and second delay controllers for receiving an input signal;
• a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object circuits.

A semiconductor integrated circuit module having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object semiconductor integrated circuits.

A semiconductor integrated circuit system having:

• first and second delay controllers for receiving an input signal;
• a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line;
• and
• a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein:
• a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object semiconductor integrated circuit modules.