Flash memory wordline decoder with overerase repair

A method of manufacturing a flash memory wordline decoder comprising the steps of:

• forming a plurality of voltage terminals to receive a plurality of voltages;
• forming a plurality of address terminals to receive a plurality of address signals;
• forming a procedure terminal to receive a procedure signal;
• forming a plurality of output wordlines adapted to be coupled to a bank of flash transistors;
• and
• forming a decoder circuit coupled to said voltage terminals, said address terminals and said procedure terminal and configured to decode said address signals, said decoder circuit including a plurality of latches coupled to said wordlines and configured to selectively latch said wordlines and to simultaneously provide different operational voltages on different ones of said wordlines to accomplish a predetermined operation responsive to said procedure signal.

A method of retrieving information from a flash memory comprising the steps of:

• receiving a plurality of voltages;
• receiving a plurality of address signals;
• receiving a procedure signal;
• decoding said address;
• latching a first set of wordlines corresponding with a first set of addresses;
• and
• applying a first operational voltage to said first set of wordlines and applying a second operational voltage to wordlines excluded from said first set to accomplish a predetermined operation responsive to said procedure signal.

A flash memory wordline decoder with overerase protection comprising:

• a plurality of voltage terminals to receive a plurality of voltages;
• a plurality of address terminals to receive a plurality of address signals;
• a procedure terminal to receive a procedure signal;
• a plurality of output wordlines adapted to be coupled to a bank of flash transistors;
• and
• a decoder circuit coupled to said voltage terminals, said address terminals and said procedure terminal and configured to decode said address signals, said decoder circuit including a plurality of latches coupled to said wordlines and configured to latch a first set of a plurality of said wordlines and to simultaneously apply a first voltage on said first set of wordlines and a different voltage on wordlines excluded from said first set to accomplish a predetermined operation responsive to said procedure signal.

A method of retrieving information from a flash memory comprising the steps of:

• receiving a plurality of voltages;
• receiving a plurality of address signals;
• receiving a procedure signal;
• decoding said address;
• latching a first set of a plurality of wordlines and simultaneously applying a first voltage on said first set of wordlines and a different voltage on wordlines excluded from said first set to accomplish a predetermined operation responsive to said procedure signal.