Systems, methods and computer program products for prediction of defect-related failures in integrated circuits

A method of predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process according to a circuit layout for an integrated circuit design, the method comprising the following steps which are performed in a data processing system:

• identifying objects in the circuit layout, each object having an object type, a location in the circuit layout and a reliability connectivity in the integrated circuit design;
• providing a process flaw distribution associated with the integrated circuit fabrication process, the process flaw distribution representing a statistical distribution of flaws produced by the integrated circuit fabrication process;
• generating sample flaws according to the process flaw distribution, each of the sample flaws having a location with respect to the circuit layout;
• correlating the locations of the sample flaws with the locations of the identified objects to thereby generate sample object defects, each sample object defect representing a defect induced in an object by a sample flaw, each sample object defect having a defect magnitude associated therewith;
• identifying an accelerated life defect influence model for each sample object defect, each accelerated life defect influence model representing an influence of the defect magnitude of a defect on the lifetime of an object;
• generating sample object lifetimes for the identified objects from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerated life defect influence models;
• and
• generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout from the sample object lifetimes according to the reliability connectivity of the associated identified objects in the integrated circuit design.

A computer program product, comprising:

• a computer-readable storage medium having computer-readable program code means embodied in said medium, said computer-readable program code means comprising:
• first computer-readable program code means for storing a circuit layout for an integrated circuit design;
• second computer-readable program code means, responsive to said first computer-readable program code means, for identifying objects in the circuit layout, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design;
• third computer-readable program code means, responsive to said second computer-readable program code means, for generating sample object defects for the identified objects, each sample object defect representing a defect induced in an object by an integrated circuit fabrication process producing integrated circuits according to the circuit layout, each sample object defect having a defect magnitude associated therewith;
• fourth computer-readable program code means, responsive to said third computer-readable computer program code means, for identifying an accelerated life defect influence model for each sample object defect, each accelerated life defect influence model relating the lifetime of an object to the defect magnitude of a defect in the object;
• fifth computer-readable program code means, responsive to said third and fourth computer-readable program code means, for generating sample object lifetimes from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerated life defect influence models;
• and
• sixth computer-readable program code means, responsive to fifth computer-readable program code means, for generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout from the sample object lifetimes according to the reliability connectivity of the associated objects in the integrated circuit design.

A method of predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process according to a circuit layout for an integrated circuit design, the circuit layout including a plurality of objects, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design, the method comprising the following steps which are performed in a data processing system:

• generating sample object defects for the plurality of objects, each sample object defect representing a defect induced in an object by the integrated circuit fabrication process, each sample object defect having a defect magnitude associated therewith;
• identifying a defect influence model for each sample object defect, each defect influence model relating the reliability connectivity of an object to the defect magnitude of a defect in the object;
• generating a prediction of the reliability of instances of the plurality of objects having the sample object defects from the defect magnitudes associated with the sample object defects according to the corresponding identified defect influence models;
• and
• generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout, from the prediction of the reliability of the instances of the plurality of objects according to the reliability connectivity of the associated objects in the integrated circuit design.

A computer apparatus for predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process according to a circuit layout for an integrated circuit design, the computer apparatus comprising:

• means for storing the circuit layout;
• means, responsive to said means for storing the circuit layout, for identifying objects in the circuit layout, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design;
• means, responsive to said means for identifying objects, for generating sample object defects for the identified objects, each sample object defect representing a defect induced in an object by the integrated circuit fabrication process, each sample object defect having a defect magnitude associated therewith;
• means, responsive to said means for generating sample object defects, for identifying an accelerated life defect influence model for each sample object defect, each accelerated life defect influence model relating the lifetime of an object to the defect magnitude of a defect in the object;
• means, responsive to said means for generating sample object defects and to said means for identifying an accelerated life defect influence model, for generating sample object lifetimes from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerate life defect influence models;
• and
• means, responsive to said means for generating sample object lifetimes, for generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout from the sample object lifetimes according to the reliability connectivity of the associated objects in the integrated circuit design.

A computer apparatus for predicting defect-related failures in integrated circuits produced by an integrated circuit fabrication process according to a circuit layout for an integrated circuit design, the apparatus comprising:

• means for storing the circuit layout;
• means, responsive to said means for storing the circuit layout, for identifying objects in the circuit layout, each object having an object type, a location and a reliability connectivity in the integrated circuit design;
• means for storing a process flaw distribution associated with the integrated circuit fabrication process, the process flaw distribution representing a statistical distribution of flaws produced by the integrated circuit fabrication process;
• means, responsive to said means for storing a process flaw distribution, for generating sample flaws according to the process flaw distribution, each of the sample flaws having a location with respect to the circuit layout;
• means, responsive to said means for identifying objects and to said means for generating sample flaws, for correlating the locations of the sample flaws with the locations of the identified objects to thereby generate sample object defects, each sample object defect representing a defect induced in an object by a sample flaw, each sample object defect having a defect magnitude associated therewith;
• means, responsive to said means for generating sample object defects, for identifying an accelerated life defect influence model for each sample object defect, each accelerated life defect influence model representing an influence of the defect magnitude of a defect on the lifetime of an object;
• means, responsive to said means for generating sample object defects and to said means for identifying a log-linear accelerated life defect influence model, for generating sample object lifetimes for the identified objects from the defect magnitudes associated with sample object defects according to the corresponding identified accelerated life defect influence models;
• and
• means, responsive to said means for generating sample object lifetimes, for generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout, from the sample object lifetimes according to the reliability connectivity of the associated identified objects in the integrated circuit design.

A computer program product, comprising:

• a computer-readable storage medium having computer-readable program code means embodied in said medium, said computer-readable program code means comprising:
• first computer-readable program code means for storing a circuit layout for an integrated circuit design;
• second computer-readable program code means, responsive to said first computer-readable program code means, for identifying objects in the circuit layout, each object having a location in the circuit layout and a reliability connectivity in the integrated circuit design;
• third computer-readable program code means for storing a process flaw distribution associated with the integrated circuit fabrication process, the process flaw distribution representing a statistical distribution of flaws produced by the integrated circuit fabrication process;
• fourth computer-readable program code means, responsive to said third computer-readable program code means, for generating sample flaws according to the process flaw distribution, each of the sample flaws having a location with respect to the circuit layout;
• fifth computer-readable program code means, responsive to said second and fourth computer-readable program code means, for correlating the locations of the sample flaws with the locations of the identified objects to thereby generate sample object defects, each sample object defect representing a defect induced in an object by an integrated circuit fabrication process producing integrated circuits according to the circuit layout, each sample object defect having a defect magnitude associated therewith;
• sixth computer-readable program code means, responsive to said fifth computer-readable computer program code means, for identifying an accelerated life defect influence model for each sample object defect, each accelerated life defect influence model relating the lifetime of an object to the defect magnitude of a defect in the object;
• seventh computer-readable program code means, responsive to said fifth and sixth computer-readable program code means, for generating sample object lifetimes from the defect magnitudes associated with the sample object defects according to the corresponding identified accelerated life defect influence models;
• and
• eighth computer-readable program code means, responsive to seventy computer-readable program code means, for generating a prediction of the reliability of integrated circuits produced by the integrated circuit fabrication process according to the circuit layout from the sample object lifetimes according to the reliability connectivity of the associated objects in the integrated circuit design.