Low voltage CMOS logic circuit with threshold voltage control
AssigneeNippon Telegraph and Telephone Corporation
InventorTakakuni Douseki
Life of this patent
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Abstract
A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits are connected between a low threshold voltage CMOS circuit and a supply voltage and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs in the MOSFET circuits are gate biased by low threshold voltage MOSFETs, thereby preventing a current from flowing across the backgate terminal and the source terminal.
Claims28
A MOSFET circuit comprising:
- a first MOSFET having a first threshold voltage;
- and
- a second MOSFET having a second threshold voltage lower than or equal to said first threshold voltage, said second MOSFET having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to an external signal, wherein said second threshold voltage is lower than said first threshold.
A CMOS logic circuit including a series connection of a load transistor and a driver transistor, one of said driver transistor and said load transistor including a first MOSFET circuit, said first MOSFET circuit comprising:
- a first MOSFET having a first threshold voltage, and being connected to the other of said driver transistor and said load transistor;
- and
- a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.
A buffer circuit including a first CMOS inverter and a second CMOS inverter alternately connected in cascade,
- wherein a load transistor of said first CMOS inverter comprises:
- a first MOSFET having a first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series;
- and
- a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and
- wherein a driver transistor of said second CMOS inverter comprises:
- a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series;
- and
- a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.
A CMOS logic circuit including a low threshold CMOS logic circuit and at least one switching circuit, said low threshold CMOS logic circuit including MOSFETs with a threshold voltage lower than a first threshold voltage, and said switching circuit being connected between a power supply terminal of said low threshold CMOS logic circuit and a power supply, wherein said switching circuit comprises:
- a first MOSFET having said first threshold voltage, and being connected between said power supply and said power supply terminal of said low threshold CMOS logic circuit;
- and
- a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.
A CMOS logic circuit comprising:
- an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal;
- a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal;
- and
- a second MOSFET connected to a second MOSFET circuit constituting the other of said set of driver transistors and said set of load transistors, wherein said second MOSFET has a same channel type as said second MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said second MOSFET circuit, and a second main current electrode connected to an inverted signal of said external control signal.
A CMOS logic circuit comprising:
- an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal;
- and
- a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal;
- wherein said internal CMOS logic circuit comprises a memory cell, and said control signal is a word line signal.
Dependencies are inferred from the claim text.