Instruction compression and decompression system and method for a processor

A method for compressing and decompressing variable length instructions contained in very long instruction word packets for a processor having a plurality of processing units, each very long instruction word packet comprising an instruction for each of said processing units, the method comprising:

• storing a plurality of said variable length instruction packets in a plurality of storage locations, each instruction packet containing compressed instructions for associated ones of said processing units;
• accessing and retrieving a selected variable length instruction packet from the storing means;
• parsing said variable length instruction packet into said compressed instructions;
• decompressing each of said compressed instructions to generate a variable length instruction for each of said associated processing units;
• and
• routing said variable length decompressed instructions from said decompression means to said associated processing units.

A system for compressing and decompressing variable length instructions contained in very long instruction word packets for a processor having a plurality of processing units, each very long instruction word packet comprising an instruction for each of said processing units, the system comprising:

• means for generating a very long instruction word packet containing instructions for corresponding ones of said processing units;
• means for assigning a compressed instruction code to each instruction within the instruction packet, the codes having different lengths and a shorter compressed instruction code being assigned to more frequently occurring instructions;
• and
• means for combining the compressed instruction codes for each instruction to generate an instruction packet having compressed instructions for corresponding ones of said processing units.

A method for compressing and decompressing variable length instructions contained in very long instruction word packets for a processor having a plurality of processing units, each very long instruction word packet comprising an instruction for each of said processing units, the method comprising:

• generating a very long instruction word packet containing instructions for each of corresponding ones of said processing units;
• assigning a compressed instruction code to each instruction within the very long word instruction packet, the codes having different lengths and a shorter compressed instruction code being assigned to more frequently occurring instructions;
• and
• combining the compressed instruction codes for each instruction to generate an instruction packet having compressed instructions for corresponding ones of said processing units.

A system for compressing and decompressing variable length instructions contained in very long instruction word packets for a processor having a plurality of processing units, each very long instruction word packet comprising an instruction for each of said processing units, the system comprising:

• means for generating a very long instruction word packet containing instructions for corresponding ones of said processing units;
• means for assigning a compressed instruction code to each instruction within the instruction packet, the codes having different lengths and a shorter compressed instruction code being assigned to more frequently occurring instructions;
• means for combining the compressed instruction codes for each instruction to generate an instruction packet having compressed instructions for corresponding ones of said processing units;
• means for storing a plurality of said variable length instruction packets in a plurality of storage locations, each instruction packet containing compressed instructions for associated ones of said processing units;
• means for accessing and retrieving a selected variable length instruction packet from the storing means;
• means for parsing said variable length instruction packet into said compressed instructions;
• means for decompressing each of said compressed instructions to generate a variable length instruction for each of said associated processing units;
• and
• means for routing said variable length decompressed instructions from said decompression means to said associated processing units.

A method for compressing and decompressing variable length instructions contained in very long instruction word packets for a processor having a plurality of processing units, each very long instruction word packet comprising an instruction for each of said processing units, the method comprising:

• generating a very long instruction word packet containing instructions for corresponding ones of said processing units;
• assigning a compressed instruction code to each instruction within the instruction packet, the codes having different lengths and a shorter compressed instruction code being assigned to more frequently occurring instructions;
• combining the compressed instruction codes for each instruction to generate an instruction packet having compressed instructions for corresponding ones of said processing units;
• storing a plurality of said instruction packets in a plurality of storage locations;
• accessing and retrieving a selected instruction packet from the storing means;
• parsing said instruction packet into said compressed instructions;
• decompressing each of said compressed instructions to generate a variable length instruction for each of said associated processing units;
• and
• routing said variable length decompressed instructions from said decompression means to said associated processing units.