Integrated circuit memory device
AssigneeMicron Technology, Inc.
InventorSteven T. Harshfield
Life of this patent
Estimating the term…
Abstract
A memory array using structure changing memory elements in a reverse biased diode array is disclosed. A memory cell is programmed and read by reverse biasing the diode to overcome the diode's breakdown voltage. The disclosed reversed biased diode array exhibits much less substrate current leakage than a similar forward biased diode array.
Claims47
A memory cell for use in an integrated circuit memory device, said memory cell comprising:
- a memory element;
- and
- a diode having a breakdown voltage and being coupled to said memory element, said memory element being programmable in response to a programming voltage having a magnitude greater than said breakdown voltage being applied across said memory element and said diode, and said memory element being readable in response to a read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage being applied across said memory element and said diode.
A memory cell for use in an integrated circuit memory device, said memory cell comprising:
- a memory element;
- and
- a diode coupled to said memory element for conducting a reverse current when said diode is reverse biased, said memory element being programmable in response to said reverse current having a first magnitude and said memory element being readable in response to said reverse current having a second magnitude.
A memory cell for use in an integrated circuit memory device, said memory cell comprising:
- a memory element;
- and
- a diode being coupled to said memory element, said memory element being programmable in response to a programming voltage being applied across said memory element and said diode, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element, and said memory element being readable in response to a read voltage being applied across said memory element and said diode, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
An integrated circuit memory device comprising:
- an array of memory cells in a common well being arranged in rows and columns;
- a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together;
- and
- a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together;
- wherein each of said memory cells comprises:
- a memory element being coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode having a breakdown voltage and having an anode coupled to receive a voltage from said one of said plurality of column lines and having a cathode coupled to receive a voltage from said one of said plurality of row lines, said memory element being programmable in response to a programming voltage having a magnitude greater than said breakdown voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, and said memory element being readable in response to a read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines.
An integrated circuit memory device comprising:
- an array of memory cells in a common well being arranged in rows and columns;
- a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together;
- and
- a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together;
- wherein each of said memory cells comprises:
- a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode conducting a reverse current when said diode is reverse biased, said memory element being programmable in response to said reverse current having a first magnitude and said memory element being readable in response to said reverse current having a second magnitude.
An integrated circuit memory device comprising:
- an array of memory cells in a common well being arranged in rows and columns;
- a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together;
- and
- a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together;
- wherein each of said memory cells comprises:
- a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said memory element being programmable in response to a programming voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element, and said memory element being readable in response to a read voltage being applied between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode having a breakdown voltage and having an anode coupled to receive a voltage from said one of said plurality of column lines and having a cathode coupled to receive a voltage from said one of said plurality of row lines, said method comprising the steps of:
- (a) programming said memory cell by applying a programming voltage between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude greater than said breakdown voltage;
- and
- (b) reading said memory cell by applying a read voltage between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude greater than said breakdown voltage and less than said programming voltage.
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said diode conducting a reverse current when said diode is reverse biased, said method comprising the steps of:
- (a) programming said memory cell by applying a reverse current having a first magnitude through said memory cell from said one of said plurality of row lines to said one of said plurality of column lines;
- and
- (b) reading said memory cell by applying a reverse current having a second magnitude through said memory cell from said one of said plurality of row lines to said one of said plurality of column lines.
A method of operating an integrated circuit memory device, said memory device having an array of memory cells in a common well being arranged in rows and columns, a plurality of electrically conductive row lines, each of said plurality of row lines coupling memory cells in a respective row together, a plurality of electrically conductive column lines, each of said plurality of column lines coupling memory cells in a respective column together, wherein each of said memory cells comprises a memory element coupled in series with a diode between one of said plurality of row lines and one of said plurality of column lines, said method comprising the steps of:
- (a) programming said memory cell by applying a programming voltage between said one of said plurality of row lines and said one of said plurality of column lines, said programming voltage having a magnitude sufficient to reverse-bias said diode and to program said memory element;
- and
- (b) reading said memory cell by applying a read voltage between said one of said plurality of row lines and said one of said plurality of column lines, said read voltage having a magnitude sufficient to reverse-bias said diode and insufficient to program said memory element.
Dependencies are inferred from the claim text.