Chip function separation onto separate stacked chips
AssigneeInternational Business Machines Corporation
InventorsClaude Louis Bertin, John Edward Cronin
Life of this patent
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Abstract
The high-voltage drivers and decoders of a direct-write EEPROM memory array are separated from the word lines and placed onto separate stacked chips. The separate chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips.
Claims49
A three-dimensional semiconductor chip having a given overall function comprised of a plurality of subfunctions, comprising:
- a first semiconductor chip comprising circuitry on a first surface thereof for performing a first portion of said plurality of subfunctions;
- a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising circuitry on a second surface thereof for performing a second portion of said plurality of subfunctions;
- and
- a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.
A three-dimensional direct-write EEPROM memory array, comprising:
- a first semiconductor chip comprising a plurality of array lines on a first surface thereof, said plurality of array lines including a plurality of direct-write EEPROM devices;
- a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising a plurality of drivers on a second surface thereof corresponding to said plurality of direct-write EEPROM devices;
- and
- a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.
A method for decreasing semiconductor chip area for a semiconductor chip having a given overall function comprised of a plurality of subfunctions, said method comprising steps of:
- separating circuitry corresponding to said plurality of subfunctions onto at least two vertically adjacent semiconductor chips;
- and
- connecting said at least two semiconductor chips, thereby forming a three-dimensional semiconductor chip.
A three-dimensional semiconductor structure having a given overall function comprised of a plurality of subfunctions, comprising:
- a first semiconductor chip comprising circuitry on a first surface thereof for performing a first subfunction of said plurality of subfunctions;
- a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising circuitry on a second surface thereof for performing a second subfunction of said plurality of subfunctions different from said first subfunction, said second surface facing said first surface;
- and
- a plurality of connectors for connecting said circuitry on said first semiconductor chip and said circuitry on said second semiconductor chip, wherein connection of said first semiconductor chip and said second semiconductor chip is essential to enable said first subfunction and said second subfunction.
Dependencies are inferred from the claim text.