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US 5,818,380 AGranted
Analog-digital converter capable of reducing a conversation error of an output signal
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMasao Ito, Takahiro Miki, Shiro Hosotani
Life of this patent
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Abstract
A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.
Claims19
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a plurality of reference potentials;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potentials include a first reference potential,
- a second reference potential lower than said first reference potential,
- a third reference potential lower than said second reference potential, and
- a fourth reference potential lower than said third reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal C.sub.i+1 indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential C.sub.i of said analog signal and said second reference potential, a third comparator outputting a third comparison result signal C.sub.i-1 indicating a result of comparison between the potential of said analog signal and said third reference potential, and
- a fourth comparator outputting a fourth comparison result signal C.sub.i-2 indicating a result of comparison between the potential of said analog signal and said fourth reference potential;
- said majority logic means includes:
- a first PMOS transistor having a gate receiving said first comparison result signal and receiving on one of its ends a power supply potential,
- a first NMOS transistor having a gate receiving said first comparison result signal and connected at one of its ends to another end of said first PMOS transistor,
- a second NMOS transistor having a gate receiving said third comparison result signal, connected at one of its ends to said first NMOS transistor and receiving on another end a ground potential,
- a second PMOS transistor having a gate receiving said second comparison result signal and receiving on one of its ends said power supply potential,
- a third NMOS transistor having a gate receiving said first comparison result signal and connected at one of its ends to a connection between said first PMOS transistor and said first NMOS transistor and another end of said second PMOS transistor,
- a fourth NMOS transistor having a gate receiving said second comparison result signal, connected at one of its ends to another end of said third NMOS transistor and receiving on another end said ground potential,
- a third PMOS transistor having a gate receiving said third comparison result signal, receiving on one of its ends said power supply potential and connected at another end to a connection between said second PMOS transistor and said third NMOS transistor,
- a fourth PMOS transistor having a gate receiving said first comparison result signal and receiving on one of its ends said power supply potential,
- a fifth PMOS transistor having a gate receiving said third comparison result signal, having an end connected to another end of said fourth PMOS transistor and having another end connected to another end of said third PMOS transistor, and
- a fifth NMOS transistor having a gate receiving said third comparison result signal, connected at one of its ends to another end of said fifth PMOS transistor and connected at another end to a connection between said third NMOS transistor and said fourth NMOS transistor, and
- said majority logic means outputs the encode output signal J.sub.i satisfying the following logical expression where indicates a logical product, v indicates a logical sum and indicates NOT:
- J.sub.i = Mi M.sub.i-1 ( 1)
- M.sub.i =(C.sub.i+1 C.sub.i) v (C.sub.i+1 C.sub.i-1) v (C.sub.i C.sub.i-1) (2)
- M.sub.i-1 =(C.sub.i C.sub.i-1) v (C.sub.i-1 C.sub.i-2) (3).
- 2.
25 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a Plurality of reference potentials;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potentials include a first reference potential,
- a second reference potential lower than said first reference potential,
- a third reference Potential lower than said second reference potential, and
- a fourth reference potential lower than said third reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal C.sub.i+1 indicating a result of comparison between the Potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential C.sub.i of said analog signal and said second reference potential,
- a third comparator outputting a third comparison result signal C.sub.i-1 indicating a result of comparison between the potential of said analog signal and said third reference potential, and
- a fourth comparator outputting a fourth comparison result signal C.sub.i-2 indicating a result of comparison between the potential of said analog signal and said fourth reference potential;
- said majority logic means outputs the encode output signal J.sub.i satisfying the following logical expression where A indicates a logical product, v indicates a logical sum and indicates NOT:
- J.sub.i = Mi M.sub.i-1 ( 1)
- M.sub.i =(C.sub.i+1 C.sub.i) v (C.sub.i+1 C.sub.i-1) v (C.sub.i C.sub.i-1) (2)
- M.sub.i-1 =(C.sub.i C.sub.i-1) v (C.sub.i-1 C.sub.i-2) (3)
- said analog/digital converter further comprises control means for outputting a first control signal and a second control signal formed of an inverted signal of said first control signal;
- said majority logic means includes:
- first switch means for outputting said received first comparison result signal in response to said second control signal,
- second switch means for outputting said received second comparison result signal in response to said second control signal,
- third switch means for outputting said received third comparison result signal in response to said second control signal,
- first capacitance means for receiving an output of said first switch means,
- second capacitance means for receiving an output of said second switch means,
- third capacitance means for receiving an output of said third switch means,
- first potential setting means for setting a potential of an input end of said first capacitance means to a ground potential in response to said first control signal,
- second potential setting means for setting a potential of an input end of said second capacitance means to said ground potential in response to said first control signal, and
- third potential setting means for setting a potential of an input end of said third capacitance means to said ground potential in response to said first control signal;
- output ends of said first to third capacitance means are commonly connected to a first node;
- said majority logic means further includes:
- fourth potential setting means for setting a potential of said first node to said ground potential in response to said first control signal, and
- inverting and amplifying means for receiving said power supply potential and said ground potential and outputting an output signal in accordance with the potential of said first node;
- and
- a logical threshold V.sub.th of said inverting and amplifying means satisfies a relationship of V/3<V.sub.th <2V/3 where V represents said power supply potential.
31 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a plurality of reference potentials;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potentials include a first reference potential,
- a second reference potential lower than said first reference potential,
- a third reference potential lower than said second reference potential, and
- a fourth reference potential lower than said third reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal C.sub.i+1 indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential C.sub.i of said analog signal and said second reference Dotential,
- a third comparator outputting a third comparison result signal C.sub.i-1 indicating a result of comparison between the potential of said analog signal and said third reference potential, and
- a fourth comparator outputting a fourth comparison result signal C.sub.i-2 indicating a result of comparison between the potential of said analog signal and said fourth reference potential;
- said majority logic means outputs the encode output signal J.sub.i satisfying the following logical expression where indicates a logical product, v indicates a logical sum and indicates NOT:
- J.sub.i = Mi M.sub.i-1 ( 1)
- M.sub.i =(C.sub.i+1 C.sub.i) v (C.sub.i+1 C.sub.i-1) v (C.sub.i C.sub.i-1) (2)
- M.sub.i-1 =(C.sub.i C.sub.i-1) v (C.sub.i-1 C.sub.i-2) (3)
- said majority logic means includes:
- first to third current supplies each receiving on one of its ends a ground potential,
- first switch means connected between another end of said first current supply and a first node and connecting said first current supply to said first node in accordance with said first comparison result signal,
- second switch means connected between another end of said second current supply and said first node and connecting said second current supply to said first node in accordance with said second comparison result signal,
- third switch means connected between another end of said third current supply and said first node and connecting said third current supply to said first node in accordane with said third comparison result signal,
- a resistance receiving on one of its ends said power supply potential and connected at another end to said first node, and
- inverting and amplifying means for receiving siad power supply potential and siad ground potential for outputting an output signal in accordance with the potential of said first node;
- and
- a logical threshold V.sub.th of siad inverting and amplifying means satisfies a relationship of V-2.multidot.R.multidot.I<V.sub.th <V-R.multidot.I where said power supply potential is V, a current value of each of said first to third current supplies is I and a resistance value of said resistance means is R.
23 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a reference potential;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potential includes a first reference potential,
- a second reference potential lower than said first reference potential, and
- a third reference potential lower than said second reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential of said analog signal and said second reference potential, and
- a third comparator outputting a third comparison result signal indicating a result of comparison between the potential of said analog signal and said third reference potential;
- and
- said majority logic means includes:
- a first PMOS transistor having a gate receiving said first comparison result signal and receiving on one of its ends a power supply potential,
- a first NMOS transistor having a gate receiving said first comparison result signal and connected at one of its ends to another end of said first PMOS transistor,
- a second NMOS transistor having a gate receiving said third comparison result signal, connected at one of its ends to said first NMOS transistor and receiving on another end a ground potential,
- a second PMOS transistor having a gate receiving said second comparison result signal and receiving on one of its ends said power supply potential,
- a third NMOS transistor having a gate receiving said first comparison result signal and connected at one of its ends to a connection between said first PMOS transistor and said first NMOS transistor and another end of said second PMOS transistor,
- a fourth NMOS transistor having a gate receiving said second comparison result signal, connected at one of its ends to another end of said third NMOS transistor and receiving on another end said ground potential,
- a third PMOS transistor having a gate receiving said third comparison result signal, receiving on one of its ends said power supply potential and connected at another end to a connection between said second PMOS transistor and said third NMOS transistor,
- a fourth PMOS transistor having a gate receiving said first comparison result signal and receiving on one of its ends said power supply potential,
- a fifth PMOS transistor having a gate receiving said third comparison result signal, having an end connected to another end of said fourth PMOS transistor and having another end connected to another end of said third PMOS transistor, and
- a fifth NMOS transistor having a gate receiving said third comparison result signal, connected at one of its ends to another end of said fifth PMOS transistor and connected at another end to a connection between said third NMOS transistor and said fourth NMOS transistor.
20 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a reference potential;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- an encoder encoding said encode output signal for outputting said digital signal;
- and
- control means for outputting a first control signal and a second control signal formed of an inverted signal of said first control signal, wherein
- said reference potential includes a first reference potential,
- a second reference potential lower than said first reference potential, and
- a third reference potential lower than said second reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential of said analog signal and said second reference potential, and
- a third comparator outputting a third comparison result signal indicating a result of comparison between the potential of said analog signal and said third reference potential;
- said majority logic means includes:
- first switch means for outputting said received first comparison result signal in response to said second control signal,
- second switch means for outputting said received second comparison result signal in response to said second control signal,
- third switch means for outputting said received third comparison result signal in response to said second control signal,
- first capacitance means for receiving an output of said first switch means,
- second capacitance means for receiving an output of said second switch means,
- third capacitance means for receiving an output of said third switch means,
- first potential setting means for setting a potential of an input end of said first capacitance means to a ground potential in response to said first control signal,
- second potential setting means for setting a potential of an input end of said second capacitance means to said ground potential in response to said first control signal, and
- third potential setting means for setting a potential of an input end of said third capacitance means to said ground potential in response to said first control signal;
- output ends of said first to third capacitance means are commonly connected to a first node;
- said majority logic means further includes:
- fourth potential setting means for setting a potential of said first node to said ground potential in response to said first control signal, and
- inverting and amplifying means for receiving said power supply potential and said ground potential and outputting an output signal in accordance with the potential of said first node;
- and
- a logical threshold V.sub.th of said inverting and amplifying means satisfies a relationship of V/3<V.sub.th <2V/3 where V represents said power supply potential.
25 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a reference potential;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potential includes a first reference potential,
- a second reference potential lower than said first reference potential, and
- a third reference potential lower than said second reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential of said analog signal and said second reference potential, and
- a third comparator outputting a third comparison result signal indicating a result of comparison between the potential of said analog signal and said third reference potential;
- said majority logic means includes:
- first to third current supplies each receiving on one of its ends a ground potential,
- first switch means connected between another end of said first current supply and a first node and connecting said first current supply to said first node in accordance with said first comparison result signal,
- second switch means connected between another end of said second current supply and said first node and connecting said second current supply to said first node in accordance with said second comparison result signal,
- third switch means connected between another end of said third current supply and said first node and connecting said third current supply to said first node in accordance with said third comparison result signal,
- a resistance receiving on one of its ends said power supply potential and connected at another end to said first node, and
- inverting and amplifying means for receiving said power supply potential and said ground potential for outputting an output signal in accordance with the potential of said first node;
- and
- a logical threshold Vth of said inverting and amplifying means satisfies a relationship of V-2.multidot.R.multidot.I<V.sub.th <V-R.multidot.I where said power supply potential is V, a current value of each of said first to third current supplies is I and a resistance value of said resistance means is R.
17 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a reference potential;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potential includes a first reference potential,
- a second reference potential lower than said first reference potential, and
- a third reference potential lower than said second reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential of said analog signal and said second reference potential, and
- a third comparator outputting a third comparison result signal indicating a result of comparison between the potential of said analog signal and said third reference potential;
- and
- said majority logic means includes
- an internal node,
- first, second and third charging means each connected to the internal node,
- control means for activating and inactivating said charging means in response to the first, second and third comparison result signals from said plurality of comparators, and
- inverting and amplifying means for providing an output signal in accordance with a potential of the internal node.
14 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a reference potential;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potential includes a first reference potential,
- a second reference potential lower than said first reference potential, and
- a third reference potential lower than said second reference potential;
- said plurality of comparators include:
- a first comparator outputting a first comparison result signal indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential of said analog signal and said second reference potential, and
- a third comparator outputting a third comparison result signal indicating a result of comparison between the potential of said analog signal and said third reference potential;
- and
- said majority logic means includes
- an internal node,
- charging means connected to the internal node for charging the internal node to a power supply potential,
- first, second and third discharging means connected to the internal node and each discharging 1/3 of the potential of the internal node,
- control means for activating and inactivating the discharging means in response to the first, second and third comparison result signals from said plurality of comparators, and
- inverting and amplifying means for providing an output signal in accordance with a potential of the internal node.
15 more elements
An analog/digital converter for converting an analog signal into a digital signal to be output, comprising:
- a plurality of comparators making comparison between a potential of said analog signal and a plurality of reference potentials;
- majority logic means for producing an encode output signal from output signals sent from said plurality of comparators using majority logic;
- and
- an encoder encoding said encode output signal for outputting said digital signal, wherein
- said reference potential includes a first reference potential,
- a second reference potential lower than said first reference potential, and
- a third reference potential lower than said second reference potential;
- said plurality of comparators includes:
- a first comparator outputting a first comparison result signal indicating a result of comparison between the potential of said analog signal and said first reference potential,
- a second comparator outputting a second comparison result signal indicating a result of comparison between the potential of said analog signal and said second reference potential,
- a third comparator outputting a third comparison result signal indicating a result of comparison between the potential of said analog signal and said third reference potential;
- and
- said majority logic means includes
- an internal node,
- a potential generating circuit, connected to said internal node, for generating four different potentials at said internal node in response to said first, second and third comparison result signals inputted from said plurality of comparators, and
- a signal outputting circuit, the input end of said signal outputting circuit connected to said internal node, for outputting an output signal having either one of a high and a low level, the output signal level of said signal outputting circuit being determined according to the potential of said internal node.
13 more elements
Dependencies are inferred from the claim text.