Semiconductor device with selectively patterned connection pad layer for increasing a contact margin

A semiconductor device comprising:

• a semiconductor substrate;
• at least one first conductivity-type MOS transistor having:
• first conductivity-type source and drain areas separately formed on said semiconductor substrate,
• a gate insulating layer formed on said semiconductor substrate between said source and drain areas, and
• a gate electrode formed on said gate insulating layer;
• a gate cover insulating layer formed over said gate electrode of said first conductivity-type MOS transistor;
• a first connection pad layer formed on said source area and a first portion of said gate cover insulating layer of said first conductivity-type MOS transistor;
• a second connection pad layer formed on said drain area and a second portion of said gate cover insulating layer of said first conductivity-type MOS transistor, said second connection pad layer being electrically insulated from said first connection pad layer;
• at least one second conductivity-type MOS transistor, said second conductivity-type being opposite said first conductivity-type, said second conductivity-type MOS transistor having:
• second conductivity-type source and drain areas separately formed on said semiconductor substrate,
• a gate insulating layer formed on said semiconductor substrate between said source and drain areas, and
• a gate electrode formed on said gate insulating layer, said first and second connection pad layers being patterned such that they are not formed over said second conductivity-type MOS transistor, and wherein no third connection pad layer is formed on said source and drain areas of said second conductivity-type MOS transistor;
• an interlevel dielectric layer having openings respectively disposed over said first and second connection pad layers and said source and drain areas of said second conductivity-type MOS transistor;
• and
• electrodes respectively connected to said first and second connection pad layers and said source and drain areas of said second conductivity-type MOS transistor through said openings.

A semiconductor memory device comprising:

• a semiconductor substrate;
• a cell array portion including:
• a plurality of first conductivity-type transistors each having a source area, a drain area and a gate, and
• a plurality of first conductivity-type connection pad layers formed on said source and drain areas of said first conductivity-type transistors to increase a contact margin;
• a peripheral circuit portion including:
• a plurality of first and second conductivity-type transistors, said first conductivity-type being opposite said second conductivity-type, said transistors each having a source area, a drain area and a gate, and
• a plurality of first conductivity-type connection pad layers formed on said source and drain areas of said first conductivity-type transistors to increase a contact margin, and wherein no second connection pad layers are formed on said source and drain areas of said second conductivity-type transistors;
• and
• an interlevel dielectric layer formed over said cell array and said peripheral circuit portions, said interlevel dielectric layer having a plurality of first openings respectively disposed over said first conductivity-type connection pad layers of said cell array and said peripheral circuit portions and a plurality of second openings respectively disposed over said source and drain areas of said second conductivity-type transistors of said peripheral circuit portion.

A semiconductor memory device comprising:

• a cell array portion;
• a peripheral circuit portion, including:
• a semiconductor substrate;
• at least one first conductivity-type area and at least one second conductivity-type area formed on said semiconductor substrate, said first conductivity-type being opposite said second conductivity-type;
• a connection pad layer formed on said first conductivity-type area and on portions of an insulating layer adjacent to said first conductivity-type area to increase a contact margin, while there is no connection pad layer formed on said second conductivity-type area;
• and
• an interlevel dielectric layer formed over said first and second conductivity-type areas, said interlevel dielectric layer having a first opening disposed over a portion of said connection pad layer formed on said first conductivity-type area and a second opening disposed over a portion of said second conductivity-type area that completely exposes said portion of said second conductivity-type area.