Resonant tunneling diode structures for funtionally complete low-power logic
AssigneeMayo Foundation for Medical Education and Research
InventorsWilliam Williamson, III, Barry Kent Gilbert
Life of this patent
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Abstract
Negative-resistance resonant tunnel diodes (RTDs) perform a complete set of logic functions with a single basic configuration. Inputs feed through Schottky diodes to a transfer RTD coupled to a clocked latch having two RTDs in series. Cascaded gates are driven synchronously by multiple clock phases or by asynchronous event signals. An XOR configuration also provides logical inversion.
Claims21
A semiconductor structure for performing any predetermined logic function of a complete logic family at high speed and low power, comprising:
- a plurality of inputs each having a separate terminal for an input signal and an isolating device coupled from said separate input terminal to the isolating device of others of said inputs to form a common input node;
- a transfer resonant tunnel diode having an anode coupled to said common input node and having a cathode coupled to an output node;
- a clock terminal for receiving a clock waveform;
- a latch having load and storage resonant tunnel diodes, said load resonant tunnel diode having an anode coupled to said clock terminal and a cathode coupled to an output node, said storage resonant tunnel diode having an anode coupled to said output node and a cathode coupled to a ground potential;
- an output terminal coupled to said output node for producing at least one output signal;
- and
- wherein the current/voltage relationships of the isolating devices and the resonant tunnel diodes are selected to determine the logical function implemented by the semiconductor.
A common-floorplan circuit personalizable to perform any selected one of a complete set of logic functions, said set including both inverting and noninverting functions, comprising:
- a first input isolating device having a first electrode for receiving a first input signal and a second electrode coupled to a common input node;
- a second input isolating device having a first electrode for receiving a second input signal and a second electrode coupled to said common input node;
- a latch having a load device and a two-terminal negative-resistance storage device, said load and storage devices being coupled together at a common output node;
- a transfer device for transferring to said latch a combination of first and second input currents from the first and second input isolating devices , respectively;
- a connection for coupling a clock signal to said latch, said clock signal having a first level for holding said common output node at a level determined by said combination during a second level of said clock signal previous in time to the first level of said clock signal;
- and
- wherein the current/voltage relationships of the isolating devices, the transfer device, the load device and the negative-resistance storage device are selected to determine the logical function implemented by the semiconductor structure.
Dependencies are inferred from the claim text.