Multi-buffered configurable logic block output lines in a field programmable gate array
AssigneeXilinx, Inc.
InventorsStephen M. Trimberger, Khue Duong
Life of this patent
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Abstract
A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.
Claims21
An output driver configuration for a logic block comprising:
- a first buffer coupled to an output port of the logic block for driving an output signal;
- a second buffer coupled to the output port of the logic block for driving the output signal;
- a first output line coupled to the first buffer;
- means for programmably coupling the first output line to one of a critical interconnect path and a non-critical interconnect path for the output signal;
- a second output line coupled to the second buffer;
- and
- means for programmably coupling the second output line to one of a critical interconnect path and a non-critical interconnect path for the output signal.
A programmable logic device comprising:
- a logic block including an input port for receiving an input signal, means for processing the input signal, and an output port for providing an output signal;
- an interconnect structure for programmably interconnecting the logic block to other portions of the programmable logic device, the interconnect structure including:
- a plurality of horizontal interconnect lines;
- a plurality of vertical interconnect lines;
- and
- a plurality of switch matrices located at some of the intersections of the horizontal and vertical interconnect lines for programmable coupling certain horizontal and vertical interconnect lines,
- a first interconnect line programmably coupled to the output port, wherein the first interconnect line becomes part of one of a critical path and a non-critical path;
- a first buffer coupled between the output port and the first interconnect line for driving the output signal on the first interconnect line;
- a second interconnect line programmably coupled to the output port, wherein the second interconnect line becomes part of one of a critical path and a non-critical path;
- and
- a second buffer coupled between the output port and the second interconnect line for driving the output signal on the second interconnect line.
In a programmable logic chip, a method of isolating a critical path that conducts a logic block output signal from non-critical paths upon which the output signal is conducted, the method comprising the steps of:
- driving the output signal onto a first line by a first buffer;
- programmably routing the output signal from the first line onto a plurality of interconnect lines, wherein the first line forms part of the non-critical paths;
- driving the output signal onto a second line by a second buffer;
- and
- programmably routing the output signal from the second line onto an interconnect line, wherein the second line forms part of the critical path, and wherein the second buffer is not loaded with the first line and the plurality of interconnect lines.
Dependencies are inferred from the claim text.