Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer

A process of fabricating a MOSFET comprising the steps of:

• forming an epitaxial layer on a surface of a semiconductor substrate, said epitaxial layer having a substantially planar top surface, both of said substrate and said epitaxial layer being doped with ions of a first conductivity type, said substrate being doped to a greater concentration level than said epitaxial layer;
• implanting ions of said first conductivity type through said top surface of said epitaxial layer so as to form a buried layer of said first conductivity type;
• forming a trench extending downward from said surface of said epitaxial layer;
• forming a dielectric layer on a wall of said trench;
• filling said trench with a conductive gate material, said gate material being electrically insulated from said epitaxial layer by said dielectric layer;
• forming a body region of a second conductivity type opposite to said first conductivity type in said epitaxial layer;
• and
• forming a source region of said first conductivity type in said epitaxial layer;
• wherein at the completion of said process an upper edge of said buried layer is at a level that is located above an interface between said substrate and said epitaxial layer and a lower edge of said buried layer is at a level that is located below said interface.

A process of fabricating a MOSFET comprising the steps of:

• forming an epitaxial layer on a surface of a semiconductor substrate, said epitaxial layer having a substantially planar top surface, both of said substrate and said epitaxial layer being doped with ions of a first conductivity type, said substrate being doped to a greater concentration level than said epitaxial layer;
• implanting ions of said first conductivity type through said top surface of said epitaxial layer so as to form a buried layer of said first conductivity type;
• forming a dielectric layer on said surface of said epitaxial layer;
• forming a gate over said dielectric layer;
• forming a body region of a second conductivity type opposite to said first conductivity type in said epitaxial layer;
• and
• forming a source region of said first conductivity type in said epitaxial layer;
• wherein at the completion of said process an upper edge of said buried layer is at a level that is located above an interface between said substrate and said epitaxial layer and a lower edge of said buried layer is at a level that is located below said interface.

A process of fabricating a MOSFET comprising the steps of:

• providing a semiconductor substrate doped with ions of first conductivity type;
• implanting ions of said first conductivity type into said substrate so as to form a layer of said first conductivity type within said substrate;
• forming an epitaxial layer on a surface of said semiconductor substrate, said epitaxial layer being doped with ions of said first conductivity type;
• allowing ions within said layer of said first conductivity type to diffuse across an interface between said substrate and said epitaxial layer;
• forming a trench extending downward from said surface of said epitaxial layer;
• forming a dielectric layer on a wall of said trench;
• filling said trench with a conductive gate material, said gate material being electrically insulated from said epitaxial layer by said dielectric layer;
• forming a body region of a second conductivity type opposite to said first conductivity type in said epitaxial layer;
• and
• forming a source region of said first conductivity type in said epitaxial layer;
• wherein at the completion of said process said layer of ions of said first conductivity type extends across an interface between said substrate and said epitaxial layer downward to a level below said interface and upward to a level above a bottom of said trench.