Sourceless floating gate memory device and method of storing data

A memory array comprising a plurality of cells, the array comprising:

• a substrate having a surface;
• a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate;
• an oxide region overlying the plurality of drain regions on the surface of the substrate;
• a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions;
• wherein data is stored on each of the plurality of cells by an addition or removal of a charge accumulation on each floating gate, such that upon application of a positive voltage to the drain, and a negative voltage to the floating gate a current between the drain and the substrate is induced in proportion to an amount of electrons stored on the gate.

A memory cell, consisting of:

• a drain region formed in a substrate;
• a gate oxide on the substrate, the gate oxide having a thickness;
• and
• a floating gate comprised of a semiconductor material on the gate oxide, the floating gate having a first and a second end, wherein the semiconductor material is tapered at said first and second ends such that the thickness of the gate oxide at the ends of the floating gate is greater than at the middle of the gate.