Method and apparatus for selecting a register file in a data processing system
AssigneeMotorola, Inc.
InventorsWilliam C. Moyer, John Arends
Life of this patent
Estimating the term…
Abstract
A data processing system selects between a general register file and an alternate register file during an operation such that resources of the data processor may be more flexibly mapped to a context of the data processing system and, therefore, be more efficiently utilized. A control bit in a processor status register (PSR) is used to select between a general register file and an alternate register file depending upon a logic value to which it is set to a during an exception handling process.
Claims12
A data processor, comprising:
- an interrupt recognition circuit which determines when an exception processing operation should be executed;
- a first register set;
- a second register set;
- a control bit which is modified during execution of the exception processing operation, the control bit selecting one of the first register set and the second register set for use during execution of a remaining portion of the exception processing operation;
- and
- a memory for storing an exception vector corresponding to the exception processing operation, wherein a first bit of the exception vector determines a logic value of the control bit.
A method for executing an exception processing operation in a data processor, comprising the steps of:
- detecting an interrupt which requires execution of the exception processing operation;
- calculating an address of a first instruction of an exception handler which corresponds to the exception processing operation;
- retrieving a data value corresponding to the address of the first instruction of the exception handler;
- modifying a first control bit in response to the data value;
- selecting a first register set for use during execution of the exception processing operation when the first control bit is in a first logic state;
- and
- selecting a second register set for use during execution of the exception processing operation when the first control bit is in a second logic state.
A data processor, comprising:
- an interrupt recognition circuit which determines when an exception processing operation should be executed;
- a first register set;
- a second register set;
- a control bit which is modified during execution of the exception processing operation, the control bit selecting one of the first register set and the second register set for use during execution of a remaining portion of the exception processing operation;
- and
- a memory for storing an exception bit corresponding to the exception processing operation, the exception bit determining a logic value of the control bit.
A data processor, comprising:
- an interrupt recognition circuit which determines when an exception processing operation should be executed;
- a first register set;
- a second register set;
- a control bit which is modified during execution of the exception processing operation, the control bit selecting one of the first register set and the second register set for use during execution of a remaining portion of the exception processing operation;
- wherein a first instruction of the exception processing operation specifies a logic value of the control bit.
Dependencies are inferred from the claim text.