Digital phase lock loop and system for digital clock recovery

A digital phase lock loop (PLL) in a data communications network for data and clock recovery of Ethernet data, the digital PLL reducing noise sensitivity and power consumption, the digital PLL comprising:

• a data extraction and end of transmission delimiter (ETD) circuit including a preamble acquisition circuit for detecting the acquisition of a preamble portion of the Ethernet data, wherein the preamble acquisition circuit further comprises a linear shift back counter, a state selection logic coupled to the linear shift back counter, and an output logic coupled to the state selection logic;
• an edge detection comparator coupled to the data extraction and ETD circuit;
• an up/down counter coupled to the edge detection comparator;
• and
• a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data.

A digital phase lock loop (PLL) in a data communications network for data and clock recovery of Ethernet data, the digital PLL reducing noise sensitivity and power consumption, the digital PLL comprising:

• a data extraction and end of transmission delimiter (ETD) circuit;
• an edge detection comparator coupled to the data extraction and ETD circuit;
• an up/down counter coupled to the edge detection comparator;
• and
• a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data, wherein the phase adjustment oscillator further comprises a counter, a sample reference adjust logic coupled to the counter, a half bit adjust logic coupled to the counter, and a multiplexor logic coupled to the half bit adjust logic and the sample reference adjust logic.

A system for data and clock recovery of Ethernet data of Manchester format in a network the system comprising:

• a digital phase lock loop (PLL) circuit, the digital PLL circuit for a) receiving the data in a data extraction and ETD circuit of the digital PLL circuit and an edge detection comparator of the digital PLL circuit;
• b) adjusting a phase of a reference clock and a sample clock to track transitions in the data;
• (c) determining whether the reference clock and data are synchronous in the edge detection comparator;
• (d) outputting an up/down adjust signal from the edge detection comparator when the data and reference clock are not synchronous;
• (e) adjusting an up/down counter from the up/down adjust signal;
• and (f) outputting an up tick or a down tick signal from the up/down counter when a predetermined count value in a predetermined count direction has been reached.

A method for data and clock recovery of Ethernet data of Manchester format in a network, the method comprising the steps of:

• a) receiving the data in a data extraction and ETD circuit of a digital PLL circuit and an edge detection comparator of the digital PLL circuit;
• b) adjusting a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL;
• c) determining whether the reference clock and data are synchronous in the edge detection comparator;
• d) outputting an up/down adjust signal from the edge detection comparator when the data and reference clock are not synchronous;
• e) adjusting an up/down counter from the up/down adjust signal;
• and
• f) outputting an up tick or a down tick signal from the up/down counter when a predetermined count value in a predetermined count direction has been reached.