Self-convergent method for programming FLASH and EEPROM memory cells that moves the threshold voltage from an erased threshold voltage range to one of a plurality of programmed threshold voltage ranges

A method for programming a memory cell having spaced-apart source and drain regions formed in a substrate material, a channel region defined between the source and drain regions, a layer of first insulation material formed over the channel region, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• and
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges by applying a substrate voltage to the substrate material, a drain voltage to the drain region, and one of a plurality of programming voltages to the control gate, each of the plurality of programming voltages corresponding to one of the plurality of remaining threshold voltage ranges, the plurality of programming voltages being negative.

A method for programming a memory cell having spaced-apart source and drain regions formed in a substrate material, a channel region defined between the source and drain regions, a layer of first insulation material formed over the channel region, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges by applying a substrate voltage to the substrate material, a drain voltage to the drain region, and one of a plurality of programming voltages to the control gate, each of the plurality of programming voltages corresponding to one of the plurality of remaining threshold voltage ranges;
• sinking a current that flows from the drain region to the substrate material during programming with a current source connected to the substrate material;
• and
• limiting a magnitude of the current with the current source.

A method for programming a memory cell having spaced-apart source and drain regions formed in a substrate material, a channel region defined between the source and drain regions, a layer of first insulation material formed over the channel region, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges by applying a substrate voltage to the substrate material, a drain voltage to the drain region, and one of a plurality of programming voltages to the control gate, each of the plurality of programming voltages corresponding to one of the plurality of remaining threshold voltage ranges;
• sourcing a current that flows from the drain region to the substrate material during programming with a current source connected to the drain region;
• and
• limiting a magnitude of the current with the current source.

A method for programming a memory cell having spaced-apart source and drain regions formed in a substrate material, a channel region defined between the source and drain regions, a layer of first insulation material formed over the channel region, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• and
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges by applying a substrate voltage to the substrate material, a drain voltage to the drain region, and one of a plurality of programming voltages to the control gate, each of the plurality of programming voltages corresponding to one of the plurality of remaining threshold voltage ranges
• wherein the substrate material is a well of a first conductivity type formed in a substrate of a second conductivity type.

A method for programming a memory cell having spaced-apart source and drain regions formed in a substrate material, a channel region defined between the source and drain regions, a layer of first insulation material formed over the channel region, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• and
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges by applying a substrate voltage to the substrate material, a drain voltage to the drain region, and one of a plurality of programming voltages to the control gate, each of the plurality of programming voltages corresponding to one of the plurality of remaining threshold voltage ranges, wherein when the substrate voltage, the drain voltage, and one of the programming voltages are applied, electrons flow from the floating gate to the drain region via Fowler-Nordheim tunneling.

A method for programming a memory cell having spaced-apart source, first drain, and second drain regions formed in a substrate material, a first channel region defined between the source and first drain regions, a second channel region defined between the first and second drain regions, a layer of first insulation material formed over the first channel region having a thin portion and a thick portion, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, a control gate formed over the layer of second insulation material, a layer of third insulation material formed over the second channel region, and a select gate formed over the layer of third insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• and
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges by applying a substrate voltage to the substrate material, a select voltage to the select gate, a drain voltage to the second drain region, and one of a plurality of programming voltages to the control gate, each of the plurality of programming voltages corresponding to one of the plurality of remaining threshold voltage ranges.

A method for programming a memory cell having spaced-apart source and drain regions formed in a substrate material, a channel region defined between the source and drain regions, a layer of first insulation material formed over the channel region, a floating gate formed over the layer of first insulation material, a layer of second insulation material formed over the floating gate, and a control gate formed over the layer of second insulation material, the method comprising the steps of:

• defining a plurality of threshold voltage ranges having a first threshold voltage range and a plurality of remaining threshold voltage ranges, the plurality of threshold voltage ranges defining a corresponding plurality of logic states;
• setting a threshold voltage of the memory cell to fall within the first threshold voltage range, the first threshold voltage range defining a first logic state of the plurality of logic states;
• and
• changing the threshold voltage to fall within one of the plurality of remaining threshold voltage ranges after the threshold voltage has been set to fall within the first threshold voltage range by applying biasing voltages to the memory cell that cause the threshold voltage to settle to a voltage which is bounded by one of the remaining threshold voltage ranges,
• wherein carriers, defined as majority carriers in the drain region, are injected onto the floating gate, and removed from the floating gate, at the same time at a substantially equal rate when the threshold voltage settles to the voltage which is bounded by one of the remaining threshold voltage ranges.