Glitch free clock enable circuit

A glitch free clock enable circuit for use in a digital system having a source of an input clock signal of first and second characteristics, a source of a clock enable signal of said first and second characteristics, and a source of a fixed state signal, said glitch free clock enable circuit comprising:

• a first storage circuit operable to generate a first output signal of said first and second characteristics;
• a second storage circuit operated in response to said input clock signal changing from said second characteristic to said first characteristic and said fixed state signal to generate a second output signal of said first characteristic, and further operated in response to said first output signal of said first characteristic to generate said second characteristic of said second output signal while said first output signal is of said first characteristic, and further operated in response to said first output signal of said first characteristic to generate a third output signal of a said first characteristic while said first output signal is of said first characteristic, and further operated in response to said input clock signal changing from said second characteristic to said first characteristic and said fixed state signal to generate said second characteristic of said third output signal;
• said first storage circuit operated in response to said input clock signal changing from said first characteristic to said second characteristic and said clock enable signal of said first characteristic to generate said first output signal of said first characteristic, and further operated in response to said input clock signal changing from said first characteristic to said second characteristic and said clock enable signal of said second characteristic to generate said first output signal of said second characteristic, and further operated in response to said third output signal of said first characteristic to generate said first output signal of said second characteristic while said third output signal is of said first characteristic, and further operated in response to said input clock signal changing from said first characteristic to second characteristic and said clock enable signal of said second characteristic to generate a fourth output signal of said first characteristic, and further operated in response to said input clock signal changing from said first characteristic to said second characteristic and said clock enable signal of said first characteristic to generate said second characteristic of said fourth output signal, and further operated in response to said third output signal of said first characteristic to generate said fourth output signal of said first characteristic while said third output signal is of said first characteristic;
• and
• a combinatorial logic circuit operated in response to said second output signal of said first characteristic and said fourth output signal of said first characteristic to generate a clock output signal of a said first characteristic, and further operated in response to said second output signal of said second characteristic or said fourth output signal of said second characteristic to generate said clock output signal of said second characteristic.