Controller having a fail safe function, automatic train controller and system using the same

A controller comprising a first serial converter for converting a parallel input signal to a serial signal;

• a first processor for processing said serial signal of said first serial converter;
• a first parallel converter for converting a serial output signal of said first processor to a parallel signal;
• a second serial converter for converting a parallel input signal to a serial signal;
• a second processor for processing said serial signal of said second serial converter;
• a second parallel converter for converting a serial output signal of said second processor to a parallel signal;
• a first status discrimination signal for discriminating the statuses of said first serial converter, said first processor, and said first parallel converter;
• means for providing a second status discrimination signal for discriminating the statuses of said second serial converter, said second processor, and said second parallel converter;
• means for providing a first failure detection signal for indicating the statuses of said first serial converter, said first processor, and said first parallel converter in response to said first status discrimination signal;
• means for providing a second failure detection signal for indicating the statuses of said second serial converter, said second processor, and said second parallel converter in response to said second status discrimination signal;
• polarity inversion failure detection signal generating means for generating a polarity inversion failure detection signal by inverting the output polarity of said second failure detection signal;
• a first adder for adding said first status discrimination signal and said polarity inversion failure detection signal;
• and a second adder for adding said second status discrimination signal and said first failure detection signal;
• an output signal of said first adder being supplied to said first serial converter together with said parallel input signal and an output signal of said second adder being supplied to said second serial converter together with said parallel input signal.

A controller comprising a first processor for outputting a first detection signal and a first output signal which is obtained by inputting and processing a first input signal and a polarity inversion detection signal;

• a second processor for outputting a second detection signal and a second output signal which is obtained by inputting and processing a second input signal and said first detection signal;
• a first connection for supplying said first detection signal to said second processor;
• and a second connection for supplying said polarity inversion detection signal of said second processor to said first processor;
• wherein said second processor outputs said second detection signal on the basis of said first detection signal inputted via said first connection, and said second connection outputs a polarity inversion detection signal, obtained by inverting the polarity of said second detection signal, to said first processor;
• and wherein said first processor outputs said first detection signal on the basis of said polarity inversion detection signal.

An ATP device comprising a first logic unit, including a first failure detector for checking first control data including at least two kinds of CRC data according to an ATP command speed signal for instructing the speed of an electric motor vehicle using one of said CRC data and for outputting a first failure detection signal, a first frequency converter for converting said first control data to a first ATP command speed frequency signal, and a first frequency comparator for comparing a speed frequency signal which is proportional to a detected speed of said electric motor vehicle and said first ATP command speed frequency signal and for outputting a first output signal according to a deviation between said speed frequency signal and said first ATP command speed frequency signal;

• a second logic unit, including a second failure detector for checking second control data including at least two kinds of CRC data according to said ATP command speed signal using one of said CRC data and outputting a second failure detection signal, a second frequency converter for converting said second control data to a second ATP command speed frequency signal, and a second frequency comparator for comparing said speed frequency signal and said second ATP command speed frequency signal and for outputting a second output signal according to the deviation between said speed frequency signal and said second ATP command speed frequency signal;
• and a matcher for correlating said first output signal and said second output signal and outputting alternating signals;
• said CRC data of said second failure detector being changed by said first failure detection signal and said CRC data of said first failure detector being changed by said second failure detection signal.

An ATP device comprising a first microcomputer responsive to an ATP command speed signal for instructing the speed of an electric motor vehicle for generating first control data including at least two kinds of CRC data;

• a second microcomputer responsive to said ATP command speed signal for generating second control data including at least two kinds of CRC data;
• a first logic unit, including a first failure detector for checking said first control data inputted from said first microcomputer using one of said CRC data and for outputting a first failure detection signal, a first frequency converter for converting said first control data to an ATP command speed frequency signal, and a frequency comparator for comparing a speed frequency signal which is proportional to the speed of said electric motor vehicle and said ATP command speed frequency signal and for outputting a first output signal according to a deviation between said speed frequency signal and said ATP command speed frequency signal;
• a second logic unit, including a second failure detector for checking said second control data inputted from said second microcomputer using one of said CRC data and for outputting a second failure detection signal, a second frequency converter for converting said second control data to an ATP command speed frequency signal, and a frequency comparator for comparing said speed frequency signal of said electric motor vehicle and said ATP command speed frequency signal and for outputting a second output signal according to a deviation between said speed frequency signal and said ATP command speed frequency signal;
• and a matcher for correlating said first output signal and said second output signal and for outputting alternating signals;
• said CRC data of said second control data being changed by said first failure detection signal and said CRC data of said first control data being changed by said second failure detection signal.

An automatic train control system comprising a generator which is installed outside an electric motor vehicle for generating an ATP command speed signal for instructing the speed of said electric motor vehicle;

• a receiver which is installed inside said electric motor vehicle for receiving said ATP command speed signal from said generator;
• a speed detector which is installed inside said electric motor vehicle for detecting a speed of said electric motor vehicle and for generating a speed frequency signal in proportion to said speed;
• and an ATP device which is installed inside said electric motor vehicle for controlling the speed of said electric motor vehicle using said ATP command speed signal and said speed frequency signal;
• said ATP device comprising:
• a first microcomputer responsive to said ATP command speed signal outputted from said receiver for generating first control data including at least two kinds of CRC data;
• a second microcomputer responsive to said ATP command speed signal outputted from said receiver for generating second control data including at least two kinds of CRC data;
• a first logic unit, including a first failure detector for checking said first control data inputted from said first microcomputer using one of said CRC data and for outputting a first failure detection signal, a first frequency converter for converting said first control data inputted from said first microcomputer to an ATP command speed frequency signal, and a frequency comparator for comparing said speed frequency signal and said ATP command speed frequency signal and for outputting a first output signal according to a deviation therebetween;
• a second logic unit including, a second failure detector for checking said second control data inputted from said second microcomputer using one of said CRC data and for outputting a second failure detection signal, a second frequency converter for converting said second control data inputted from said second microcomputer to an ATP command speed frequency signal, and a frequency comparator for comparing said speed frequency signal and said ATP command speed frequency signal and for outputting a second output signal according to the deviation therebetween;
• and
• a matcher connected to receive said first failure detection signal, said first output signal, said second failure detection signal, and said second output signal, for correlating said first output signal and said second output signal on the basis of said first and second failure detection signals, and for outputting alternating signals in which said first output signal and said second output signal alternate;
• and
• a braking device which is installed inside said electric motor vehicle and which is responsive to said alternating signals, for controlling a braking force applied to said electric motor vehicle;
• said CRC data of said second failure detector being changed by said first failure detection signal and said CRC data of said first failure detector being changed by said second failure detection signal.

An ATP device comprising:

• a first microcomputer responsive to an ATP command speed signal for instructing the speed of an electric motor vehicle and for generating first control data together with first CRC data and second control data together with second CRC data;
• a second microcomputer for generating third control data together with third CRC data and fourth control data together with fourth CRC data;
• a first logic unit, including a first memory for storing said first control data outputted from said first microcomputer, a second memory for storing said second control data, a first switching circuit for switching said first memory and said second memory, a first failure detector and a second failure detector for checking output data of said first switching circuit, a first adder for adding said output data of said first switching circuit and an output signal of said second failure detector, a second adder for adding a speed frequency signal which is proportional to a speed of said electric motor vehicle and an output signal of said first failure detector, a first frequency converter for converting an output signal of said first adder to an ATP command speed frequency signal, and a first frequency comparator for comparing an output signal of said second adder and an output signal of said first frequency converter and for outputting a first output signal and a first failure detection signal according to a deviation therebetween;
• a second logic unit, including a third memory for storing said third control data outputted from said second microcomputer, a fourth memory for storing said fourth control data, a second switching circuit for switching said third memory and said fourth memory, a third failure detector and a fourth failure detector for checking output data of said second switching circuit, a third adder for adding said output data of said second switching circuit and an output signal of said fourth failure detector, a fourth adder for adding a speed frequency signal which is proportional to a speed of said electric motor vehicle and an output signal of said third failure detector, a second frequency converter for converting an output signal of said third adder to an ATP command speed frequency signal, and a second frequency comparator for comparing an output signal of said fourth adder and an output signal of said second frequency converter and for outputting a second output signal and a second failure detection signal according to a deviation therebetween;
• and a matcher for correlating said first output signal of said first logic unit, said second output signal of said second logic unit, said first failure detection signal, and said second detection signal, respectively, and for outputting alternating signals, wherein said first failure detection signal controls said second switching circuit and switches said third control data and said fourth control data, and wherein said second failure detection signal controls said first switching circuit said first switching circuit and switches said first control data and said second control data.