US 5,802,555 A · Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method

Abstract

A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit. A RAS multiplexer has inputs for an output of the refresh RAS circuit and for data access RAS, and has an output connected to RAS output terminals of the memory controller for connection to an external dynamic random access memory to effect refresh. The microprocessor unit, which may be integrated onto a single integrated circuit chip with the refresh and memory controller, has a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes configuration registers and circuitry for controlling the access thereto, including circuitry for determining memory address type and bank sizes.

Claims29

Dependent claims

A refresh controller circuit in a single chip memory controller responsive to a stop request from a microprocessor and also having row address strobe (RAS) output terminals for connection to an external memory, the refresh controller circuit comprising:

an idle condition detector for detecting an idle condition responsive to absence of memory read or write requests for a period of time;
a refresh queue counter circuit;
a refresh clock circuit;
a control latch for storing at least one bit indicative of a self refresh mode enable and at least one other bit indicative of a refresh queuing enable;
a self refresh circuit which is enabled by said self refresh mode enable and has an input coupled to said refresh clock circuit;
a suspend enable circuit coupled to an output of said idle condition detector and to a stop request line;
a refresh row address strobe circuit having an output, and a first input coupled to an output of said self refresh circuit and a second input coupled to an output of said suspend enable circuit;
and
a row address strobe multiplexer having an output coupled to said RAS output terminals and a first input for data access RAS and a second input coupled to the output of said refresh row address strobe circuit.

6 more elements

A refresh controller circuit comprising:

an idle condition detector for detecting an idle condition responsive to absence of memory read or write requests for a period of time;
a refresh clock circuit for generating a refresh clock signal;
a self refresh circuit having an input receiving the refresh clock signal, having an input for receiving a self refresh mode signal, and having an output for presenting the refresh clock signal responsive to the self refresh mode signal indicating that self refresh mode is not enabled, and for presenting a row address strobe disable state responsive to the self refresh mode signal indicating that self refresh mode is enabled;
a suspend enable circuit, having an input coupled to the idle condition detector and having an input for receiving a stop request signal, for generating a suspend signal responsive to receiving the stop request signal during an idle condition;
a suspend refresh row address strobe circuit having a first input coupled to the output of the self refresh circuit and having a second input coupled to receive the suspend signal, for generating at least one row address strobe signal corresponding to the output of the self refresh circuit responsive to receiving the suspend signal;
and
a row address strobe generator circuit, for generating row address strobe signals to a memory, the row address strobe generator circuit comprising a multiplexer having a first input for receiving a row address strobe signal corresponding to data accesses, having a second input coupled to the output of the suspend refresh row address strobe circuit, and having a control input for receiving a signal corresponding to the suspend signal, for forwarding, to a memory, at least one row address strobe signal corresponding to the output of the suspend refresh row address strobe circuit responsive to the suspend signal.

4 more elements

A computer system comprising:

a memory;
a memory bus coupled to said memory, comprising lines for communicating address, data, and control signals, the control signals comprising at least one row address strobe signal and at least one column address strobe signal;
a microprocessor unit, comprising:
a microprocessor having a processing unit operable to process digital data in accordance with computer instructions;
a memory controller, coupled to the microprocessor, and coupled to the memory via the memory bus, comprising:
an idle condition detector for detecting an idle condition responsive to absence of memory read or write requests from the microprocessor for a period of time;
a refresh clock circuit for generating a refresh clock signal;
a self refresh circuit having an input receiving the refresh clock signal, having an input for receiving a self refresh mode signal, and having an output for presenting the refresh clock signal responsive to the self refresh mode signal indicating that self refresh mode is not enabled, and for presenting a row address strobe disable state responsive to the self refresh mode signal indicating that self refresh mode is enabled;
a suspend enable circuit, having an input coupled to the idle condition detector and having an input for receiving a stop request signal, for generating a suspend signal responsive to receiving the stop request signal during an idle condition;
a suspend refresh row address strobe circuit having a first input coupled to the output of the self refresh circuit and having a second input coupled to receive the suspend signal, for generating at least one row address strobe signal corresponding to the output of the self refresh circuit responsive to receiving the suspend signal;
and
a row address strobe generator circuit, for generating row address strobe signals to the memory, the row address strobe generator circuit comprising a multiplexer having a first input for receiving a row address strobe signal corresponding to data accesses requested by the microprocessor, having a second input coupled to the output of the suspend refresh row address strobe circuit, and having a control input for receiving a signal corresponding to the suspend signal, for forwarding, to the memory, at least one row address strobe signal corresponding to the output of the suspend refresh row address strobe circuit responsive to the suspend signal;
a peripheral processor unit coupled to said microprocessor unit and having circuitry for bidirectional data communication therewith;
a user input interface coupled to the peripheral processor unit;
and
an output interface coupled to the peripheral processor unit.

13 more elements

A method of operating a computer system having a microprocessor and a memory, to control the refresh of the memory, comprising the steps of:

monitoring memory read requests and memory write requests;
responsive to the monitoring step detecting the absence of memory read requests and memory write requests over a period of time, and responsive to a suspend request signal from the microprocessor, generating a suspend acknowledge signal;
generating a refresh clock signal corresponding to a refresh period of the memory;
interrogating a control store to determine whether the memory is of self-refresh type;
responsive to the interrogating step determining that the memory is not of self-refresh type, applying the refresh clock signal to an input of a refresh row address strobe circuit;
responsive to the interrogating step determining that the memory is of self-refresh type, applying the refresh clock signal to an input of a refresh row address strobe circuit;
responsive to the interrogating step determining that the memory is of self-refresh type, blocking the refresh clock signal from the input of the refresh row address strobe circuit and instead applying an enable signal to the input of the refresh row address strobe circuit;
and
responsive to the suspend acknowledge signal, controlling the refresh row address strobe circuit to generate at least one row address strobe signal to the memory corresponding to the signal applied at its input.

6 more elements

Dependencies are inferred from the claim text.

Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method

Life of this patent

Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method

Life of this patent

Abstract

Claims29