Microprocessor capable of unpacking packed data
AssigneeIntel Corporation
InventorsAlexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Abstract
A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
Claims11
A processor comprising;
- a storage area to store a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in said first plurality of data elements corresponds to a different data element in said second plurality of data elements, in a respective position;
- a decoder to decode an unpack instruction;
- and
- a circuit, coupled to said storage area and said decoder, said circuit simultaneously copies less than all data elements from said first plurality of data elements and corresponding data elements from the second plurality of data elements into said storage area as a third plurality of separate data elements in a third packed data in response to the unpack instruction.
A computer system comprising;
- a processor;
- and
- a storage area coupled to said processor having stored therein,
- an unpack instruction for operating on a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in said first plurality of data elements corresponds to a different data element in said second plurality of data elements, in a respective position,
- said processor, in response to receiving the unpack instruction, simultaneously copies less than all data elements from said first plurality of data elements and corresponding data elements from the second plurality of data elements into said storage area as a third plurality of separate data elements in a third packed data.
An apparatus for use in a computer system comprising:
- a storage area means for storing a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in said first plurality of data elements corresponds to a different data element in said second plurality of data elements, in a respective position;
- a decoder means for decoding an unpack instruction;
- and
- a circuit means, coupled to said storage area means and said decoder means, said circuit means for simultaneously coping less than all data elements from said first plurality of data elements and corresponding data elements from the second plurality of data elements into said storage area as a third plurality of separate data elements in a third packed data in response to the unpack instruction.
Dependencies are inferred from the claim text.